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SKY-8260S Manual V02 20220411
Copyright 2022 Advantech Co. Ltd. All rights reserved.
Page 42
- 64-bit wide Channels plus 8-bits of ECC Support for Each Channel
- DRAM Density : 1Gb, 2Gb, 4Gb, 8Gb,
- Integrated Dual SMBus Master Controllers
2.4.6.2 DDR4 DIMM Location and SMBus Mapping
Always insert memories in DIMM 1 first. After all the DIMM1 slots are occupied, and then
DIMM 0 can be inserted with memories.
DIMM 1 (Blue socket): D2, D4, D6, D8, D10, D12, D14, D16
DIMM 0 (Black socket): D1, D3, D5, D7, D9, D11, D13, D15
Table 2-13: AMD EPYC
TM
Processor DDR4 DIMM SMBus Address List
Location
CPU/Channel
H/W Address
Device Address
D1
CPU1 / CHA DIMM0 SA[2:0]=000
A0
D2
CPU1 / CHA DIMM1 SA[2:0]=001
A2
D3
CPU1 / CHB DIMM0 SA[2:0]=010
A4
D4
CPU1 / CHB DIMM1 SA[2:0]=011
A6
D5
CPU1 / CHC DIMM0 SA[2:0]=100
A8
D6
CPU1 / CHC DIMM1 SA[2:0]=101
AA
D7
CPU1 / CHD DIMM0 SA[2:0]=110
AC
D8
CPU1 / CHD DIMM1 SA[2:0]=111
AE
D9
CPU1 / CHE DIMM0 SA[2:0]=000
A0
D10
CPU1 / CHE DIMM1 SA[2:0]=001
A2
D11
CPU1 / CHF DIMM0 SA[2:0]=010
A4
D12
CPU1 / CHF DIMM1 SA[2:0]=011
A6
D13
CPU1 / CHG DIMM0 SA[2:0]=100
A8
D14
CPU1 / CHG DIMM1 SA[2:0]=101
AA
D15
CPU1 / CHH DIMM0 SA[2:0]=110
AC
D16
CPU1 / CHH DIMM1 SA[2:0]=111
AE
