SKY-8232D Manual V02 20220411
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Page 43
2.4.6.2 DDR4 DIMM Location and SMBus Mapping
Always insert memories in DIMM 1 slots first. After all the DIMM1 slots are occupied, and
then DIMM 0 can be inserted with memories.
CPU0 always has to contain at least one DIMM to power on the system. If only one DIMM
needs to insert, insert at any of CPU0 DIMM1 slots (blue sockets). If more than one DIMM
needs to insert, insert at least one DIMM at CPU0 DIMM1 slot.
Also, it is recommended that the number of memories are balanced between CPU0 and
CPU1 (i.e. if there are 8 memories, insert 4 at CPU 0 and 4 at CPU1).
DIMM 0 (Black socket): D1, D3, D5, D7, D9, D11, D13, D15
DIMM 1 (Blue socket): D2, D4, D6, D8, D10, D12, D14, D16
Finally, to optimize the performance of the system, insert only one DIMM per channel.
Table 2-12: Third Gen Intel® Xeon® Scalable processors DDR4 DIMM SMBus
Address List
Location
CPU/Channel
H/W Address
Device Address
D1
CPU0/ CPU1 CHA DIMM0
SA[2:0]=000
A0
D2
CPU0/ CPU1 CHA DIMM1
SA[2:0]=001
A2
D3
CPU0/ CPU1 CHB DIMM0
SA[2:0]=010
A4
D4
CPU0/ CPU1 CHB DIMM1
SA[2:0]=011
A6
D5
CPU0/ CPU1 CHC DIMM0
SA[2:0]=100
A8
D6
CPU0/ CPU1 CHC DIMM1
SA[2:0]=101
AA
D7
CPU0/ CPU1 CHD DIMM0
SA[2:0]=110
AC
D8
CPU0/ CPU1 CHD DIMM1
SA[2:0]=111
AE
D9
CPU0/ CPU1 CHE DIMM0
SA[2:0]=000
A0
D10
CPU0/ CPU1 CHE DIMM1
SA[2:0]=001
A2
D11
CPU0/ CPU1 CHF DIMM0
SA[2:0]=010
A4
D12
CPU0/ CPU1 CHF DIMM1
SA[2:0]=011
A6
D13
CPU0/ CPU1 CHG DIMM0
SA[2:0]=100
A8
D14
CPU0/ CPU1 CHG DIMM1
SA[2:0]=101
AA
D15
CPU0/ CPU1 CHH DIMM0
SA[2:0]=110
AC
D16
CPU0/ CPU1 CHH DIMM1
SA[2:0]=111
AE
