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PCM-3753I User Manual

10

Using Jumpers to Set Ports as Output Ports

By shorting the two pins of the jumpers JPA0, JPB0, JPC0L, JPC0H, 
JPA1, JPB1, JPC1L, JPC1H, JPA2, JPB2, JPC2L, JPC2H, JPA3, JPB3, 
JPC3L or JPC3H, a user sets the corresponding ports to be output ports. 
(JPA0 means jumper for port A0, JPB0 means jumper for port B0, etc.)  
Shorting the two pins of a port's jumper disables the port from being soft-
ware configurable as an input port.  The initial state of each of these ports 
after system power on or reset will be logic 0 (voltage low), unless 
jumper JP1 determines otherwise. (See JP1 below.)

Jumper JP1 Restores Ports to Their Condition Prior to Reset

Jumper JP1 gives the PCM-3753I a new and valuable capability.  With 
JP1 enabled (i.e., by shorting the lower two pins of JP1), the 
PCM-3753I "memorizes" all port I/O settings and output values, and, in 
the event of a "hot" reset, the settings and output values present at the port 
just prior to reset are restored to each port following reset.  This feature 
applies to both ports set by software, and to ports configured as output 
ports via jumper.  Depending on the application, this capability may allow 
a card to be reset without requiring a complete shutdown of processes 
controlled by the card (since port values are left unchanged and are inter-
rupted only momentarily). 
Complete loss of power to the chip clears chip memory.  Thus, even if 
JP1 is enabled, if the power to the card is disconnected, the card's initial 
power-on state will be the state of an input port with voltage high input 
(for software-set ports) or the state of an output port with voltage low out-
put (for jumper-set ports). 
When jumper JP1 is not enabled both power-off and reset results in ports 
returning to the state of an input port with voltage high input or returning 
to the state of output port with voltage low output (for jumper-set ports).

Table 2.1: Summary of Jumper Settings

Jumpers

Function Description

JP1

Keep the last digital output    
status after hot reset

JP1

Load default configuration while 
hot  reset  (Default)

Summary of Contents for PCM-3753I

Page 1: ...PCM 3753I 96 channel Digital I O PCI 104 Module User Manual...

Page 2: ...Advantech Co Ltd assumes no responsibility for its use nor for any infringements of the rights of third parties which may result from its use Acknowledgments PC LabCard is a trademark of Advantech Co...

Page 3: ...lacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem enc...

Page 4: ...lem The exact wording of any error messages Packing List Before setting up the system check that the items listed below are included and in good condition If any item does not accord with the table pl...

Page 5: ...4 3 2 Digital I O Ports 14 3 2 1 Introduction 14 3 2 2 8255 Mode 0 14 3 2 3 Input Output Control 15 Table 3 1 Bitmap of Port Configuration Register 15 3 2 4 Initial Configuration 15 3 2 5 Dry Contact...

Page 6: ...PCM 3753I User Manual vi...

Page 7: ...2 CHAPTER 1 General Information...

Page 8: ...l input channel at the PCM 3753I accepts either 0 5 VDC wet contact or dry contact inputs This dry contact capability allows the channel to respond to changes in external circuitry e g the closing of...

Page 9: ...ard with more capability and flexibility The PCM 3753I also provides Pattern Match interrupt function for port A0 The card monitors the states of port A0 and compares them with a pre set pattern When...

Page 10: ...n match and Change of state interrupt functions for critical I O monitoring Keeps I O setting and digital output values when hot system reset Supports dry contact and wet contact 50 pin pin header Boa...

Page 11: ...V max 24 mA sink Logic level 1 3 76 V min 24 mA source Transfer Rate 1 6 Mbytes sec tested under DOS K6 300MHz CPU Power Consumption 5 V 105 mA typical 5 V 210 mA max Operating Temperature 0 60 C 32...

Page 12: ...PCM 3753I User Manual 6 1 5 Pin Assignments CN5 CN8 CN5 A0 B0 C0 CN6 A1 B1 C1 CN7 A2 B2 C2 CN8 A3 B3 C3...

Page 13: ...2 CHAPTER 2 Installation...

Page 14: ...rton and packing materials for inspection by the carrier We will then make arrangements to repair or replace the unit 2 2 Unpacking The PCM 3753I contains components that are sensitive and vulnerable...

Page 15: ...t Ports as Input or Output by Software When the two pins of jumpers JPA0 JPB0 JPC0L JPC0H JPA1 JPB1 JPC1L JPC1H JPA2 JPB2 JPC2L JPC2H JPA3 JPB3 JPC3L or JPC3H are not shorted i e by setting a jumper t...

Page 16: ...rt just prior to reset are restored to each port following reset This feature applies to both ports set by software and to ports configured as output ports via jumper Depending on the application this...

Page 17: ...tory If you need to adjust this setting please see below 2 4 1 BoardID Register You can determine the BoardID setting in the register as shown below Table 2 2 BoardID Setting SW2 BoardID DEC Switch Po...

Page 18: ...connector J1 of the PCM 3753I card to the PCI 104 con nector Carefully align the pins with the PC 104 connector Slide the module into the connector The module pins may not slide all the way into the c...

Page 19: ...2 CHAPTER 3 Operation...

Page 20: ...er driving capability than a standard 8255 chip Each of these 8255 chip emulators has 24 programmable I O pins that are divided into three 8 bit ports The total 96 digital I O pins on the PCM 3753I is...

Page 21: ...ts configured by software are automatically set as input ports during system start up or reset with a default signal level of logic 1 high All ports set via jumpers as output ports are set as output p...

Page 22: ...s the channel to respond to changes in external circuitry e g the closing of a switch in the external circuitry when no voltage is present in the external circuit Figure 3 1 shows external circuitry w...

Page 23: ...y 3 3 2 IRQ Level The IRQ level is set automatically by the PCI plug and play BIOS and is saved in the PCI controller There is no need for users to set the IRQ level Only one IRQ level is used by this...

Page 24: ...01 pattern patch interrupt flag bit of port A0 F02 change of state interrupt flag bit of port B0 Table 3 2 Interrupt Control Register Bitmap Base 16 48 Port 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 Abbreviation...

Page 25: ...Interrupt Sources M01 M00 0 0 0 1 1 0 1 1 PC00 PC04 M11 M10 0 0 0 1 1 0 1 1 PC10 PC14 M21 M20 0 0 0 1 1 0 1 1 PC20 PC24 M31 M30 0 0 0 1 1 0 1 1 PC30 PC34 M2 1 0 M1 1 0 Change of State PB0 Pattern Matc...

Page 26: ...Base 49 determines the interrupt source of port C1 and so forth Please refer the table in Appendix A to find the corresponding address for the interrupt source control of each port C The following tab...

Page 27: ...t Read the bit s value to find the status of the interrupt write 1 to this bit to clear the interrupt This bit must be cleared in the ISR to service the next incoming interrupt F01 pattern patch inter...

Page 28: ...ern match function for the I O channels PA01 PA02 PA06 and PA07 of the PCM 3753I is enabled i e PA00 PA03 PA04 and PA05 on the PCM 3753I and port A0 on the PCM 3753IE are ignored during the pattern ma...

Page 29: ...t function for the I O channels PB01 PB02 PB06 and PB07 on the PCM 3753IE are enabled i e the signals in PB00 PB03 PB04 and PB05 on the PCM 3753IE and port B0 of the PCM 3753I are ignored during the c...

Page 30: ...PCM 3753I User Manual 24...

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