Advantech PCI-1751, User Manual

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17 PCI-1751 User Manual
Chapter 3
S
ignal Connections
Interrupt Triggering Edge Control
The interrupt can be triggered by a rising edge or a falling edge of the interrupt signal,
selectable by the value written in the "triggering edge control" bit in the interrupt con-
trol register, as shown in Table 3.6.
Interrupt Flag Bit
The "interrupt flag" bit is a flag indicating the status of an interrupt. It is a readable
and writable bit. Read the bit value to find the status of the interrupt, write "1" to this
bit to clear the interrupt. This bit must be cleared in the ISR to service the next
incoming interrupt.
Table 3.5: Interrupt Mode Bit Values
Port 1 Port 0
M11 M10 Description M01 M00 Description
0 0 Disable interrupt 0 0 Disable interrupt
0 1 Source = PC10 0 1 Source = PC00
1 0 Source = PC10 & PC14 1 0 Source = PC00 & PC04
1 1 Source = Counter 2 1 1 Source = Counter 1
Table 3.6: Triggering Edge Control Bit Values
E0 or E1 Triggering edge of interrupt signal
1 Rising edge trigger
0 Falling edge trigger
Table 3.7: Interrupt Flag Bit Values
F0 & F1 Interrupt status
Read 1 Interrupt exists
0 No interrupt
Write 1 Clear interrupt
0 Don’t care