Advantech MIC-3399 User Manual Download

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MIC-3399 User Manual

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2.3.3.1

CPU Configuration

Figure 2.12 CPU Configuration



Hyper-Threading

This item allows users to enable/disable the CPU hyper-threading function. The

default setting is enabled for Windows XP and Linux (OS optimized for hyper-

threading technology) and disabled for other OS (OS is not optimized for hyper-

threading technology).



Execute Disable Bit

XD can prevent certain classes of malicious buffer overflow attacks when com

bined with a supporting OS. (Windows Server 2003 SP1, Windows XP SP2,

SuSE Linux 9.2, RedHat Enterprise 3 Update 3.)



Hardware Prefetcher

This item allows users to enable/disable the MLC streamer prefetcher.



Adjacent Cache Line Prefetch

This item allows users to enable/disable the prefetching of adjacent cache lines.

Summary of Contents for MIC-3399

Page 1: ...User Manual MIC 3399 6U CompactPCI Blade SBC with 6th Gen Intel Core i3 i5 i7 Processor and Optional ECC Memory...

Page 2: ...warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most customers never need to use our repair service If an Advantech product is defec...

Page 3: ...interference In this event users are required to correct the interference at their own expense FM This equipment has passed the FM certification According to the National Fire Pro tection Association...

Page 4: ...1 x Solder side cover assembled 1 x RJ45 to DB9 cable 1 x Warranty certificate If any of the above items are missing or damaged contact your distributor or sales representative immediately Warning Wa...

Page 5: ...ur liquid into an opening This may cause fire or electrical shock 13 Never open the equipment For safety reasons the equipment should be opened only by qualified service personnel 14 If any of the fol...

Page 6: ...ing Do not touch any components on the CPU card or other cards while the PC is powered on Disconnect the power before making any configuration changes A sudden rush of power after connecting a jumper...

Page 7: ...re I O Input output IC Integrated circuit I2C Inter integrated circuit IPMB Intelligent platform management bus IPMI Intelligent platform management interface KCS Keyboard controller style LPC Low pin...

Page 8: ...MIC 3399 User Manual viii...

Page 9: ...lock Diagram 8 1 4 Jumpers and Switches 8 Table 1 4 Jumper Descriptions 8 Table 1 5 Switch Descriptions 8 1 4 1 Jumper Settings 9 Table 1 6 JCMOS1 Clear RTC 9 Table 1 7 JLVDS1 Settings 9 1 4 2 Switch...

Page 10: ...Figure 2 16PCI Subsystem 32 Figure 2 17Graphics Configuration 33 Figure 2 18LCD Control 34 Figure 2 19Southbridge 35 Figure 2 20SATA Configuration 36 Figure 2 21NCT6126D Super I O Configuration 37 Fi...

Page 11: ...Defaults Command 62 Table 3 12 Reload NVRAM Defaults Command 62 3 8 5 Write MAC Address Command 63 Table 3 13 Write MAC Address Command 63 3 8 6 Store Configuration Command 64 Table 3 14 Store Config...

Page 12: ...XMC1 Connector 79 A 7 Front I O Connector 80 Table A 8 VGA1 Connector 80 Table A 9 RJ45 LAN1 LAN2 Connector 80 Table A 10 USB3CN1 USB3CN2 USB3CN3 80 Table A 11 COM1 RJ45 Connector 80 Table A 12 BH1 C...

Page 13: ...Chapter 1 1 Hardware Configuration This chapter describes how to configure the MIC 3399 hardware...

Page 14: ...cifications MIC 3399 supports 64 bit PCI bus extensions 66 33 MHz for up to six CompactPCI slots at 3 3 V or 5 V VIO 1 2 Specifications 1 2 1 CompactPCI Bridge MIC 3399 uses a Pericom PI7C9X130 univer...

Page 15: ...el chipsets The Intel CM236 chipset offers up to 8 GT s for fast access to peripheral devices and supports high bandwidth interfaces such as PCI Express Gen III Serial ATA Gen III and Hi Speed USB 2 0...

Page 16: ...ansition module PICMG 2 16 1 2 6 Storage Interface MIC 3399 provides up to six SATA III interfaces with RAID 0 1 5 10 support Two SATA interfaces are routed to the onboard 2 5 SATA daughter board only...

Page 17: ...ll payload and application related circuitry However it does not reset the system management IPMI related circuitry A separate BMC reset button on the front panel is provided for BMC and related hardw...

Page 18: ...ffers a wide variety of I O including four RJ45 LAN one RJ45 COM two DVI one USB 3 0 one USB 2 0 one P S2 in the rear panel one COM pin header four USB 2 0 pin headers and two SATA connectors RIO 3316...

Page 19: ...d to the X86 payload 1 2 18 Super I O The MIC 3399 super I O device provides the following legacy PC features Serial port COM1 and COM2 are connected to J5 and can be accessed via the rear I O module...

Page 20: ...and switch settings on the MIC 3399 board Table 1 4 Jumper Descriptions Number Function Note JCMOS1 Clear CMOS JLVDS1 Rear LVDS power voltage setting Table 1 5 Switch Descriptions Number Function Note...

Page 21: ...and 3 as per the Normal setting 4 Power on the system The BIOS will be restored to the default settings JCMOS1 Closed 1 2 JCMOS1 Closed 2 3 1 4 1 2 Rear LVDS Setting JLVDS1 This jumper is used to con...

Page 22: ...ront panel to the rear I O 1 4 2 3 PCI Bridge Master Drone Mode SW2 3 This switch is used to switch the PCI bridge between Master and Drone modes Table 1 8 SW2 1 Switch VGA Output Status Function Note...

Page 23: ...4 2 5 PCIE Bus Settings SW4 This switch is used to configure the PCIe mode settings Table 1 11 SW2 4 Drone Mode Settings Status Function Note Off Drone mode w o J1_RST default On Drone Mode w J1_RST...

Page 24: ...witch Settings These switches are only available for the RIO 3316 C1E model Table 1 13 SW3 and SW4 for Internal COM1 Status Function Note Default RS 232 RS 422 RS 485 Table 1 14 SW5 and SW6 for COM2 S...

Page 25: ...nstalling a board may damage sensitive electronic components Always ground yourself to remove any static charge before touching the CPU board Be particularly careful not to touch the chip connectors M...

Page 26: ...ector pins We recommend that you perform assembly at an antistatic workbench 1 7 1 HDD Installation MIC 3399 supports a 2 5 SATA hard disk drive The SATA HDD daughter board is pre assembled on the MIC...

Page 27: ...x M3 screws to fasten them in place Figure 1 5 Attach the SATA HDD to the HDD brackets 2 Install the SATA HDD attached to the brackets into the chassis Connect the SATA HDD to the SATA connector Faste...

Page 28: ...ment batteries can be purchased from Advantech Contact your local sales represen tative to check availability 1 9 Software Support MIC 3399 has been tested and verified to support Windows 7 10 Linux...

Page 29: ...Chapter 2 2 AMI BIOS Setup This chapter describes how to configure the AMI BIOS...

Page 30: ...IC 3399 that allows users to modify the basic system configuration and function settings The BIOS Setup program features a number of menus for adjusting various items This chapter describes the basic...

Page 31: ...figuration settings However when the CMOS battery is removed or the clear CMOS jumper is set all settings will be restored to the default BIOS settings 2 3 Entering the BIOS When the system is powered...

Page 32: ...ot be configured whereas items presented in blue text can be configured The right frame displays the key legend Located above the key legend is an area reserved for a text message When an item is sele...

Page 33: ...ck on the Platform tab to enter the Platform setup menu Users can click on the items in the left frame of the screen such as Serial Console to access the submenu for that item Use the and keys to move...

Page 34: ...Manual 22 2 3 2 1 Serial Console Setting Figure 2 5 Serial Console Setting Console Redirection This item allows users to enable disable console redirection or Microsoft Win dows Emergency Management...

Page 35: ...3 MIC 3399 User Manual Chapter 2 AMI BIOS Setup 2 3 2 2 Firmware Update Figure 2 6 Firmware Update ME FW Image Re Flash This item allows users to enable disable the ME firmware image re flash func tio...

Page 36: ...devices are connected The disable option will keep USB devices available only for EFI applications The default setting is enabled EHCI Hand Off This is a workaround for operating systems without EHCI...

Page 37: ...is item allows users to enable disable storage hierarchy Endorsement Hierarchy This item allows users to enable disable endorsement hierarchy TPM2 0 UEFI Spec Version This item allows users to select...

Page 38: ...ble Intel Virtualization Technology When enabled a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology Intel VT d This item allows users to enable disable VT d capab...

Page 39: ...nagement EIST This item allows users to configure the system to support more than two fre quency ranges Package C State Limit This item allows users to configure the maximum package C state limit CPU...

Page 40: ...al 28 2 3 3 Hardware Settings Select the Hardware tab to enter the Hardware setup menu Users can select any item in the left frame of the screen to access the submenu for that item Figure 2 11 Hardwar...

Page 41: ...ology and disabled for other OS OS is not optimized for hyper threading technology Execute Disable Bit XD can prevent certain classes of malicious buffer overflow attacks when com bined with a support...

Page 42: ...MIC 3399 User Manual 30 2 3 3 2 Northbridge Figure 2 13 Northbridge 2 3 3 3 Memory Configuration Figure 2 14 Memory Configuration This page shows the memory information...

Page 43: ...limit Watts is calculated by multiplying this value by the slot power limit scale Values 0 255 PEG0 1 2 Slot Power Limit Scale This item allows users to select the scale used for the slot power limit...

Page 44: ...system Settings Figure 2 16 PCI Subsystem Above 4G Decoding This item allows users to enable disable the decoding of 64 bit capable devices in above 4G address space this option is only available is t...

Page 45: ...he setup options GTT Size This item allows users to select the GTT size Aperture Size This item allows users to select the aperture size NOTE Above 4GB MMIO BIOS assignment is automatically enabled wh...

Page 46: ...ws users to set the Active LFP configuration settings No LVDS VBIOS does not enable LVDS Int LVDS VBIOS enables the LVDS driver via the integrated encoder SDVO LVDS VBIOS enables the LVDS driver via t...

Page 47: ...35 MIC 3399 User Manual Chapter 2 AMI BIOS Setup 2 3 3 8 Southbridge Figure 2 19 Southbridge...

Page 48: ...lows users to enable disable SATA devices SATA Controller Speed This item allows users to configure the maximum speed the SATA controller can support and to enable disable SATA port 1 port 2 port 3 po...

Page 49: ...37 MIC 3399 User Manual Chapter 2 AMI BIOS Setup 2 3 3 10 NCT6126D Super I O Configuration Figure 2 21 NCT6126D Super I O Configuration Figure 2 22 SIO Uart1 to RJ45...

Page 50: ...Uart1 mode to front I O RJ45 J3 or BMC Uart1 When SIO Uart1 to RJ45 is selected the BMC Uart1 switch mode will be set to J3 automatically When SIO Uart1 to BMC J3 is selected the BMC Uart1 switch mod...

Page 51: ...39 MIC 3399 User Manual Chapter 2 AMI BIOS Setup Figure 2 24 Serial Port Mode Serial Port1 Mode This item allows users to set the serial port1 mode as RS 232 RS 422 or RS 485...

Page 52: ...MIC 3399 User Manual 40 2 3 3 11 Serial Port 1 Configuration Figure 2 25 Serial Port1 Configuration Serial Port This item allows users to enable disable the serial port COM...

Page 53: ...l Port 2 Configuration Figure 2 26 Serial Port 2 Configuration Serial Port This item allows users to enable disable the serial port COM Serial Port2 Mode This item allows users to set the serial Port2...

Page 54: ...MIC 3399 User Manual 42 2 3 3 13 Serial Port 3 Configuration Figure 2 27 Serial Port 3 Configuration Serial Port This item allows users to enable disable the serial port COM...

Page 55: ...43 MIC 3399 User Manual Chapter 2 AMI BIOS Setup 2 3 3 14 Serial Port 4 Configuration Figure 2 28 Serial Port 4 Configuration Serial Port This item allows users to enable disable the serial port COM...

Page 56: ...MIC 3399 User Manual 44 2 3 3 15 H W Monitor Configuration Figure 2 29 H W Monitor configuration This page shows the PC heath status information...

Page 57: ...g timer If enabled the system will start a BIOS timer that can only be shut off by management software after the OS loads The OS watchdog timer helps determine whether the OS has successfully loaded o...

Page 58: ...en set to on the keyboard numlock state will stay on after booting When set to off the keyboard numlock state will stay off after booting Quiet Boot This item allows users to enable disable the quiet...

Page 59: ...ws users to set the display mode for option ROM GateA20 Active This item allows users to enable disable GA20 active status This option is use ful when any RT code is executed above 1 MB When configure...

Page 60: ...riority Network This item allows users to configure the execution of the UEFI and legacy PXE option Storage This item allows users to configure the execution of the UEFI and legacy stor age OpROM Vide...

Page 61: ...49 MIC 3399 User Manual Chapter 2 AMI BIOS Setup 2 3 6 Security Figure 2 34 Security Settings Password Check Password Check Set password check mode Administrator Password Set administrator password...

Page 62: ...ore the default values for the setup options The BIOS automatically configures all setup items to optimal settings when users select this option Defaults are designed for maximum system performance bu...

Page 63: ...Chapter 3 3 IPMI Configuration This chapter describes IPMI con figuration for MIC 3399...

Page 64: ...wn hardware abstraction layer HAL and IPMI stack The BMC s key features and functions are listed below Advantech Integrity Sensor Based on the Advantech IPMI core and designed for CompactPCI IPMI 2 0...

Page 65: ...Field replaceable unit GbE Gigabit Ethernet GPIO General purpose input output HPM 1 Hardware platform management 1 I2C Inter integrated circuit IPMB Intelligent platform management bus IPMI Intellige...

Page 66: ...messaging interface between CPCI boards It consists of one I2C bus clocked at a frequency of 100 kHz using IPMI compliant messaging 3 3 2 KCS The BMC KCS interface is implemented according to the IPMI...

Page 67: ...to from the BMC 3 3 3 3 RMCP RMCP IPMI over LAN IOL uses RMCP as the messaging protocol as defined in the IPMI specifications RMCP messages consist of the basic IPMI message with some RMCP specific o...

Page 68: ...Up Step through history bios_hist Show BIOS POST code history cpci_payload Get CPCI payload power status date Display current date and time debug Enable and select debug options help Print command ove...

Page 69: ...does not modify the watchdog timer except for two situations It disables the watchdog right before jumping into the boot loader to avoid trig gering after BIOS execution It can alternatively reconfigu...

Page 70: ...GRITY C0h 70h Advantech Integrity OEM sensor 10 POWER_GOOD 08h 6Fh IPMI Power Supply sensor 11 HOT_5_0 VOL 02h 01h Standby Power CPCI voltage 5 V 12 SB_5_0 VOL 02h 01h Payload Power voltage 5 V 13 MAN...

Page 71: ...pper non recoverable UCR Upper critical UNC Upper non critical LNC Lower non critical LCR Lower critical LNR Lower non recoverable Table 3 5 Voltage Sensor List Sensor Name Nominal LNR LCR LNC UNC UCR...

Page 72: ...the supported event code structure gen erated by the integrity sensors on MIC 3399 Table 3 6 Temperature Sensor List Sensor Name Nominal LNR LCR LNC UNC UCR UNR PCH TMP 40 100 104 CPU TMP 50 100 110 H...

Page 73: ...antech s IANA Enterprise Number used for OEM commands is 002839h The BMC supports all Advantech IPMI OEM commands listed in the table below 3 8 1 Set Multiplexer Command This command is used to set mu...

Page 74: ...he next reboot The command is only allowed when payload power is off Table 3 10 Get Multiplexer Command Byte Data Field Request Data 1 3 Advantech IANA ID 392800h 4 Multiplexer selection 00h 02h reser...

Page 75: ...e non BMC MAC addresses are written during manufacturing and are only MAC address copies for the mirroring feature This means there is no change to the real HW MAC device Table 3 13 Write MAC Address...

Page 76: ...h Bios 04h Lan controller 05h Failure retries 06h Miscellaneous 07h RTC 08h FPGA 09h USB 0Ah Clock E keying 0Bh PCIe 0Ch BMC CLI 0Dh IRQ 0Eh Carrier Manager 5 Setting Bios 00h Switch Bios Flash Settin...

Page 77: ...PGA COM1 UART multiplexer 00h not connected 01h Serial over LAN 02h Front panel RJ45 03h RTM 1 FPGA BMC UART multiplexer 00h not connected 01h Front panel RJ45 02h RTM 1 CLI BMC UART Baud rate 00h 960...

Page 78: ...RTC 08h FPGA 09h USB 0Bh PCIe 0Ch BMC CLI 0Dh IRQ 0Eh Carrier Manager 5 Port Setting BIOS 00h Active BIOS Flash Setting LAN controller 00h LAN interface selection front rear IO Retries Reserved Settin...

Page 79: ...ltiplexer 00h not connected 01h Serial over LAN 02h Front panel RJ45 03h RTM 1 FPGA BMC UART multiplexer 00h not connected 01h Front panel RJ45 02h RTM 1 CLI BMC UART Baud rate 00h 9600 01h 14400 02h...

Page 80: ...Advantech IANA ID 392800h 4 MAC address number 00h Intel R I210 LAN1 MAC 01h Intel R I210 LAN2 MAC 02h Intel R I210 LAN3 MAC 03h Intel R I210 LAN4 MAC 04h Intel R I210 LAN5 MAC 05h BMC NCSI MAC Respo...

Page 81: ...n to the LPC1768 flash directly This means there is no recovery existing for the bootloader image It is not recommended to upgrade the bootloader in the field 3 9 2 Firmware Upgrade The firmware upgra...

Page 82: ...1 Field Description Board Information Format version 0x01 Board area length calculated Language code 0x19 English Manufacturer date time based on manufacturing date Board manufacturer type length 0xC9...

Page 83: ...m Mfg Info fields unused C1h no more info fields 0xC1 00h unused space 0x00 0x00 0x00 0x00 0x00 Board area checksum calculated Table 3 22 Board Info Area SKU3 Field Description Board Information Forma...

Page 84: ...Product part model number type length 0XCB Product part model number MIC 3399 Product version type length 0XC6 Product version Hardware Version Product serial number type length 0xCA Product serial nu...

Page 85: ...Appendix A A Pin Assignments This appendix provides the pin assignments...

Page 86: ...D 3 3V IPMB_SCL IPMB_SDA GND PERR GND 16 GND DEVSEL PCIXCAP V I O STOP LOCK GND 15 GND 3 3V FRAME IRDY BD_SEL TRDY GND 12 14 KEY AREA 11 GND AD 18 AD 17 AD 16 GND C BE 2 GND 10 GND AD 21 GND 3 3V AD 2...

Page 87: ...D AD 35 AD 34 AD 33 GND AD 32 GND 13 GND AD 38 GND V I O AD 37 AD 36 GND 12 GND AD 42 AD 41 AD 40 GND AD 39 GND 11 GND AD 45 GND V I O AD 44 AD 43 GND 10 GND AD 49 AD 48 AD 47 GND AD 46 GND 9 GND AD 5...

Page 88: ...X6 TAP_TCK PCIE_x 8_RX6 PCIE_x 8_RX6 GND 8 GND PCIE_CLK USB3_TX5 TAP_TRST USB3_TX4 USB3_RX4 GND 9 GND PCIE_CLK USB3_TX5 TAP_TDI USB3_TX4 USB3_RX4 GND 10 GND PCIE_x 8_TX7 PCIE_x 8_TX7 TAP_TDO USB3_RX5...

Page 89: ...SATA2_TX LVDS0_D3 GND DDI2_TX3 DDPC_D DC_SDA GND 11 GND GND LVDS0_D3 GND DDI2_TX3 DDPC_HPD GND 12 14 15 GND GND LVDS1_ CLK GND GND_AU DIO MIC_L GND 16 GND SATA3_RX LVDS1_CLK GND NC MIC_R GND 17 GND S...

Page 90: ...C_USB8 VGA_DAT GND 11 GND DDI3_TX1 GND J5_KBDAT USB2_D8 VGA_CLK GND 12 GND DDI3_TX2 GND J5_KBCLK USB2_D8 J5_V GAPWR GND 13 GND DDI3_TX2 GND DDP D_HPD GND VGA_VS GND 14 GND DDI3_TX3 GND LAN3_LINK 1000...

Page 91: ..._P2 PERX_N2 3 3V PERX_P3 PERX_N3 VPWR 5V 4 GND GND NC GND GND NC 5 PERX_P4 PERX_N4 3 3V PERX_P5 PERX_N5 VPWR 5V 6 GND GND NC GND GND 12V 7 PERX_P6 PERX_N6 3 3V PERX_P7 PERX_N7 VPWR 5V 8 GND GND NC GND...

Page 92: ...DDC_CLK 8 GND Table A 9 RJ45 LAN1 LAN2 Connector 1 LAN_0 5 LAN_2 2 LAN_0 6 LAN_1 3 LAN_1 7 LAN_3 4 LAN_2 8 LAN_3 Table A 10 USB3CN1 USB3CN2 USB3CN3 USB3CN1 USB3CN2 USB3CN3 1 5V fused 2 USBD1 3 USBD1 4...

Page 93: ...Swappable LEDs Table A 13 Front Panel LED Indicators Name Description M D Green Indicates Master or Drone mode status PWR Green Indicates power status HDD Yellow Indicates HDD Read Write Hot Swap Blue...

Page 94: ...MIC 3399 User Manual 82...

Page 95: ...Appendix B B Programming the Watchdog Timer This appendix describes how to program the watchdog timer...

Page 96: ...interval The value range is from 01 hex to FF hex and the related time interval is 1 to 255 seconds Data Time Interval 01 1 sec 02 2 sec 03 3 sec 04 4 sec 3F 63 sec The countdown starts by writing a v...

Page 97: ...Appendix C C FPGA Specifications This appendix describes FPGA configuration...

Page 98: ...S Interface Standard IPMI payload interface from x86 to BMC Watchdog Debug Message Boot time POST message C 3 FPGA I O Registers The MIC 3399 FPGA communicates with the main I O spaces The LPC unit is...

Page 99: ...87 MIC 3399 User Manual Appendix C FPGA Specifications...

Page 100: ...e subject to change without notice No part of this publication may be reproduced in any form or by any means such as electronically by photocopying recording or otherwise without prior written permiss...

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