Advantech IDK-1115WP-45FHA1, User Manual

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IDK-1115WP User Manual 26
3.6 Display Timing Specifications
The input signal timing specifications are shown as the following table and timing dia -
gram.
Signal Item Symbol Min. Typ. Max. Unit Note
LVDS Clock
Frequency Fc 60 70.93 75 MHz
Period Tc - 14.1 - ns
Input cycle to
cycle jitter
Trcl -0.02*Tc - 0.02*Tc ns (3)
Input clock to
data skew
TLVCCS -0.02*Tc - 0.02*Tc ns (4)
Spread spec -
trum modula -
tion range
Fclkin_
mod
FC*98% - FC*102% MHz
(5)
Spread spec -
trum modula -
tion
frequency
FSSM - - 200 KHz
Vertical Dis -
play Term
Frame Rate Fr 50 60 60 Hz Tv=Tvd+Tvb
Total Tv 1090 1110 1130 Th
Active Dis -
play
Tvd 1080 1080 1080 Th
Blank Tvb Tv-Tvd 30 Tv-Tvd Th
Horizontal Dis -
play Term
Total Th 1050 1065 1075 Tc Th=Thd+Thb
Active
Display
Thd 960 960 960 Tc
Blank Thb Th-Thd 105 Th-Thd Tc
Note(1)! Because this module is operated by DE only mode, Hsync and Vsync
input signals are ignored.
Note(2)!
The Tv(Tvd+Tvb) must be integer, otherwise, this module would operate
abnormally.