Advantech ARK-3380, User Manual

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ARK-3380 User Manual 38
4.2.4 Advanced Chipset Features
Note: The “Advanced Chipset Features” options control the configura-
tion of the board’s chipset. This page is developed for the particular
chipset, to control chipset register settings, and fine tune system perfor-
mance. It is strongly recommended that only technical users make
changes to the default settings.
• DRAM Timing Selectable [By SPD]
This option refers to the method by which the DRAM timing is
selected.
The default is “By SPD”.
Manual This item provides DRAM clock/drive for The user selec-
tion.
By SPD This item provides DRAM clock/drive for SPD (Serial Pres-
ence Detect).
• MGM Core Frequency [Auto Max 266 MHz]
This field sets the frequency of the DRAM memory installed. The
default setting is Auto Max 266MHz.
• System BIOS Cacheable [Enabled]
This item allows the system BIOS to be cached to allow faster execu-
tion and better performance.
• Video BIOS Cacheable [Disabled]
This item allows the video BIOS to be cached to allow faster execution
and better performance.
• Memory Hole [Disabled]
This item reserves 15 MB-16 MB memory address space to ISA expan-
sion cards that specifically require the setting. When enabled, memory
from 15 MB-16 MB will be unavailable to the system because only the
expansion cards can access memory in this area.
• Delayed Transaction [Enabled]
The chipset has an embedded 32-bit posted write buffer to support
delay transaction cycles. Select Enabled to support compliance with
PCI specification version 2.1.