ADMtek ADM5120, Datasheet, Page: 70 / 112

ADM5120 Register Description
30:16 RW Watchdog1_tmr_s
et
Watchdog1 timer set: the time out setting of timer, if
timer set is equal to timer, then it mean timer is expired.
Maximum 32767
RW Watchdog1_drop_
en Watchdog timer stop CPU port receiving:
0: disable,
1: force all to CPU packets drop if timer is expired, and
timer is cleaned
0 31
no issue flow control in ports. Auto-recover when the
4.4.51 Swap_in, offset 0xC8
Bits Type Name Description Initial value
7:0 RW Swap_din Swap_din[7:0] = Swap_dout[31:24]
15:8 RW Swap_din Swap_din[15:8] = Swap_dout[15:8]
23:16 RW Swap_din Swap_din[23:16] = Swap_dout[15:8]
RW Swap_din Swap_din[31:24] = Swap_dout[7:0] 31:24
4.4.52 Swap_out, offset 0xCc
Bits Type Name Description Initial value
7:0 RO Swap_dout Swap_dout[7:0] = Swap_din[31:24]
15:8 RO Swap_dout Swap_dout[15:8] = Swap_din[23:16]
23:16 RO Swap_dout Swap_dout[23:16] = Swap_din[15:8]
31:24 RO Swap_dout Swap_dout[31:24] = Swap_din[7:0]
4.4.53 send_Hbaddr, offset 0xD0
Bits Type Name Description Initial value
24:0 RW send_Hbaddr The descriptor base address of CPU_to_SW (high
priority)
Reserved 31:25 Not Applicable
Note
: the loading base addresses need all four address registers been written. (i.e.
send_Hbaddr, send_Lbaddar, receive_Hbaddar, and receive_Lbaddar)
4.4.54 send_Lbaddr, offset 0xD4
Bits Type Name Description Initial value
24:0 RW send_LBaddr The descriptor base address of CPU_to_SW (normal
priority)
31:25 Reserved Not Applicable
4.4.55 receive_Hbaddr, offset 0xD8
Bits Name Description Initial value
24:0 RW receive_HBaddr The descriptor base address of SW_to_CPU (high
priority)
Type
ADMtek Inc. 4-23