ADM5120
Register Description
RO
sel_info
If port_sel=0, [24:16] port0 high packet count [8:0]
port0 low packet count
If port_sel=1, [24:16] port1 high packet count [8:0]
port1 low packet count
If port_sel=2, [24:16] port2 high packet count [8:0]
port2 low packet count
If port_sel=3, [24:16] port3 high packet count [8:0]
port3 low packet count
If port_sel=4, [24:16] port4 high packet count [8:0]
port4 low packet count
If port_sel=5, [24:16] port5 high packet count [8:0]
port5 low packet count
If port_sel=6, [24:16] port6 high packet count [8:0]
port6 low packet count
If port_sel=7, [24:16] port7 high packet count [8:0]
port7 low packet count
If port_sel=9, [8:0] flow control status
If port_sel=10, [24:16] testing [8:0] ever flow control
port
If port_sel=11, [24:16] no_pkt status [7:0]
no_pkt_status
If port_sel=12, [24:16] receive bandwidth control port ,
[8:0] transmit bandwidth control port
4.4.45 Int_st, offset 0xB0
Note:
All bits are “write 1 clear”
Bits
Type
Description
Initial value
0
RW
send_H_done
DMA send one high priority packet to switch
1
RW
send_L_done
DMA send one normal priority packet to switch
2
RW
rx_H_done
DMA receive one high priority packet to CPU
3
RW
rx_L_done
DMA receive one normal priority packet to CPU
4 RW
H_Descriptor_full
The
descriptor, “high priority receive”, are full
5 RW
L_Descriptor_ful
the
descriptor,
“normal priority receive”, are full
6
RW
port0_que_full
meet the port0 port-th & global empty-th
7
RW
port1_que_full
meet the port1 port-th & global empty-th
RW
port2_que_full
meet the port2 port-th & global empty-th
9
RW
port3_que_full
meet the port3 port-th & global empty-th
10
RW
port4_que_full
meet the port4 port-th & global empty-th
11
RW
port5_que_full
meet the port5 port-th & global empty-th
12
Reserved
Not
Applicable
13 RW
CPU_que_full
CPU port – meet the CPU port pre-th & global empty-th
14 RW
Global_que_full
global empty-th
RW
Must_drop
Name
8
15
all the buffer almost full
ADMtek Inc.
4-20