ADLINK Technology SMARC NXP LEC-IMX8M User Manual Download | Manualshive

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LEC-iMX8M User’s Guide

SGET SMARC Rev 2.1

Page 13

copyright © 2021 ADLINK Technology Inc.

2.6

System Storage

SDIO

1x SDIO (4-bit) compatible up to version 3.0.

eMMC

soldered on module 16, 32 or 64 GB (build option) either standard or -40+85C temp range
Compatible with eMMC specification 4.41, 4.51 and 5.0

2.7

SEMA® Board Management Controller

Voltage/current monitoring, boot configuration, logistics and forensic
information, flat panel control, watchdog timer

2.8

Debug Header

30-pin multipurpose flat cable connector for use with optional DB-30 debug module Provides JTAG, BMC access; UART, power test points; diagnostic
LEDs, Power, Reset, Boot configuration

2.9

Boot Modes

eMMC and SD-Card boot modes are supported

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Summary of Contents for SMARC NXP LEC-IMX8M

Page 1: ...LEC IMX8M 01 12 2021...

Page 2: ...descriptions at any time without notice Environmental Responsibility ADLINK is committed to fulfil its social responsibility to global environmental preservation through compliance with the European U...

Page 3: ...midity Keep equipment properly ventilated do not block or cover ventilation openings Make sure to use recommended voltage and power source settings Always install and operate equipment near an easily...

Page 4: ...echnology Inc Revision History Revision Description Date dd mm yyyy Author 0 6 Preliminary engineering version 06 09 2019 JB 0 8 Preliminary engineering version updated 05 04 2020 HP 0 9 Preliminary e...

Page 5: ...9 Boot Modes 13 2 10 Power 14 2 11 Mechanical and Environmental 14 3 Block Diagram 15 4 Pinout and Signal Descriptions 16 4 1 Pin Summary 16 4 2 Signal Terminology Descriptions 20 4 3 Signal Descripti...

Page 6: ...Inc 4 4 3 CAN bus 43 4 4 4 Miscellaneous 43 4 4 5 Power and System Management 44 4 4 6 DB30 Multipurpose Connector 45 4 4 7 Boot Select 46 4 4 8 Power 47 4 5 SMARC pin to controller mapping 48 5 Softw...

Page 7: ...LEC iMX8M User s Guide SGET SMARC Rev 2 1 Page 7 copyright 2021 ADLINK Technology Inc List of Figures Figure 1 Module function diagram 15 Figure 2 Module top botom side pin numbering 17...

Page 8: ...The Module PCBs have 314 edge fingers that mate with a low profile 314 pin 0 5 mm pitch right angle connector the connector is sometimes identified as a 321 pin connector but 7 pins are lost to the k...

Page 9: ...ther as industrial 40 C to 85 C or commercial 0 C to 70 C type L2 Cache 32 KB I cache 32 KB D cache A53 16 KB I cache16 KB D cache M4 Memory 1 2 4 GB DDR3L memory down IoT security CryptoAuthenticatio...

Page 10: ...ort GPU 4 shaders OpenGL ES 3 1 OpenCL 1 2 OpenGL 3 0 OpenVG and Vulkan Up to 4kp60 UHD resolutions VPU HEVC H 265 H 264 VP9 Decoder 1080p60 MPEG 2 MPEG 4p2 VC 1 VP8 RV9 AVS MJPEG H 263 Decoder no VPU...

Page 11: ...P Precision Time Protocol and AVB Audio Video Bridging support Supports 10 100 1000 Mbps data transfer rates both full duplex and half duplex Optional Secondary LAN Intel i210 GbE controller with IEEE...

Page 12: ...0B and CAN FB mode data bit rate up to 8 Mbps via SPI to CAN controller SPI 1 x SPI optional 2 x SPI SPI0 occupied by SPI to CAN controller can be freed up by build option I2S 2x I2S interfaces with a...

Page 13: ...ible with eMMC specification 4 41 4 51 and 5 0 2 7 SEMA Board Management Controller Voltage current monitoring boot configuration logistics and forensic information flat panel control watchdog timer 2...

Page 14: ...SGET SMARC Specifications v2 1 Dimension SMARC small size module 82mm x 50mm Operating Temperature Standard 0 C to 60 C Rugged 40 C to 85 C optional Humidity 5 90 RH operating non condensing 5 95 RH...

Page 15: ...USB2 USB3 USB4 GbE0 GbE1 PCIe1 PCIe0 CAN0 ECSPI0 ECSPI1 UART0 UART1 UART3 I2S0 I2S1 SDIO GPIO I2C_GP I2C_PM NXP iMX 8M USB 2 0 OTG USB 2 0 Host USB 3 0 Host MIPI CSI 2 lanes MIPI CSI 4 lanes DSI 4 lan...

Page 16: ...and Signal Descriptions 4 1 Pin Summary The below table is a comprehensible list of all signal pins on the MXM 3 connector in the standard specification SMARC 2 1 Those signals not supported on LEC i...

Page 17: ...1 P27 GBE0_MDI1 S28 GBE1_CTREF note 1 P28 GBE0_CTREF S29 PCIE_D_TX SERDES_1_TX P29 GBE0_MDI0 S30 PCIE_D_TX SERDES_1_TX P30 GBE0_MDI0 S31 GBE1_LINK_ACT note 1 P31 SPI0_CS1 note 2 S32 PCIE_D_RX SERDES_...

Page 18: ...E1 S97 DP0_LANE1 P97 GND S98 DP0_HPD P98 HDMI_D0 DP1_LANE2 S99 DP0_LANE2 P99 HDMI_D0 DP1_LANE2 S100 DP0_LANE2 P100 GND S101 GND P101 HDMI_CK DP1_LANE3 S102 DP0_LANE3 P102 HDMI_CK DP1_LANE3 S103 DP0_LA...

Page 19: ...S144 eDP0_HPD DSI0_TE P144 CAN0_RX S145 WDT_TIME_OUT P Pin Primary Top Side S Pin Secondary Bottom Side P145 CAN1_TX S146 PCIE_WAKE P146 CAN1_RX S147 VDD_RTC P147 VDD_IN S148 LID P148 VDD_IN S149 SLE...

Page 20: ...nal for MIPI CSI 2 cameras and DSI displays LVDS M PHY Low Voltage Differential Signal for MIPI CSI 3 cameras LVDS LCD Low Voltage Differential Signal for LCD displays LVDS PCIE Low Voltage Differenti...

Page 21: ...I0_D3 DSI0_D3 eDP0_TX0 eDP0_TX0 eDP0_TX1 eDP0_TX1 eDP0_TX2 eDP0_TX2 eDP0_TX3 eDP0_TX3 S111 S112 S114 S115 S117 S118 S120 S121 LVDS1_0 LVDS1_0 LVDS1_1 LVDS1_1 LVDS1_2 LVDS1_2 LVDS1_3 LVDS1_3 DSI1_D0 DS...

Page 22: ...BKLT_EN S127 Primary LVDS channel backlight enable active high O CMOS 1 8V Runtime LCD0_BKLT_PWM S141 Primary LVDS channel brightness control through pulse width modulation PWM O CMOS 1 8V Runtime LVD...

Page 23: ...S132 S137 S138 Primary DSI panel differential pair data lines O LVDS D PHY Runtime Build option DSI0_CLK DSI0_CLK S134 S135 Primary DSI panel differential pair clock lines O LVDS D PHY Runtime Build o...

Page 24: ...LANE0 DP1_LANE1 DP1_LANE1 DP1_LANE2 DP1_LANE2 P101 P102 HDMI_CK HDMI_CK DP1_LANE3 DP1_LANE3 S105 HDMI_CTRL_CK DP1_AUX S106 HDMI_CTRL_DAT DP1_AUX P104 HDMI_HPD DP1_HPD P107 DP1_AUX_SEL Pin DP signal na...

Page 25: ...air clock lines O TMDS HDMI Runtime AC coupled off module HDMI_CTRL_CK P105 I2C_CLK line dedicated to HDMI O OD COMS 1 8V Runtime PU 2 2 Level shifter FET and 5V PU resistor shall be placed between th...

Page 26: ...T CSI0_TX S7 I2C data for serial camera data support link or differential data lane I O OD CMOS O LVDS M PHY 1 8V Runtime PU 2 2K MIPI CSI 2 0 uses I2C_CAM0_DAT MIPI CSI 3 0 uses CSI0_TX I2C_CAM0_CK C...

Page 27: ...rt link or differential data lane I O OD CMOS O LVDS M PHY 1 8V Runtime PU 2 2K MIPI CSI 2 0 mode uses I2C_CAM1_DAT MIPI CSI 3 0 mode uses CSI1_TX I2C_CAM1_CK CSI1_TX S1 I2C clock for serial camera da...

Page 28: ...ck I O CMOS 1 8V Runtime Module Output if CPU acts in Master Mode Module Input if CPU acts in Slave Mode I2S2_LRCK S50 I2S2 Left Right synchronization clock I O CMOS 1 8V Runtime Module Output if CPU...

Page 29: ...LEC iMX8M User s Guide SGET SMARC Rev 2 1 Page 29 copyright 2021 ADLINK Technology Inc 4 3 5 USB ports...

Page 30: ...port 1 I O USB USB Runtime From USB HUB USB1_EN_OC P67 USB over current sense for port 1 I O OD CMOS 3 3Vsb 3 3V Runtime PU 10k Pulled low by Module OD driver to disable USB0 power Pulled low by Carri...

Page 31: ...announce OTG device insertion on USB 3 0 port I CMOS 3 3Vsb 3 3V Runtime USB4 USB4 S35 S36 USB differential data pairs for port 4 I O USB USB Runtime USB4_EN_OC P76 USB over current sense for port 4...

Page 32: ...board PCIe clock PCIE_B_TX PCIE_B_TX S90 S91 Differential PCIe link B transmit data pair O LVDS PCIE Runtime Series AC coupled on module PCIE_B_RX PCIE_B_RX S87 S88 Differential PCIe link B receive da...

Page 33: ...untime Series AC coupled on module PCIE_D_RX PCIE_D_RX S32 S33 Differential PCIe link D receive data pair I LVDS PCIE Runtime Series AC coupled off module PCIE_WAKE S146 PCIe wake up interrupt to host...

Page 34: ...ADLINK Technology Inc LEC iMX8M User s Guide Page 34 copyright 2021 ADLINK Technology Inc 4 3 7 SATA Ports This design does not support SATA ports...

Page 35: ...RX MDI 2 B1_DC MDI 3 B1_DD GBE MDI Runtime Twisted pair signals for external transformer GBE0_LINK100 P21 Link Speed Indication LED for GBE 0 100Mbps O OD CMOS 3 3V Runtime Shall be able to sink 24mA...

Page 36: ...B1_DA TX TX MDI 1 B1_DB RX RX MDI 2 B1_DC MDI 3 B1_DD GBE MDI Runtime Twisted pair signals for external transformer GBE1_LINK100 S19 Link Speed Indication LED for GBE 1 100Mbps O OD CMOS 3 3V Runtime...

Page 37: ...Response This signal is used for card initialization and for command transfers During initialization mode this signal is open drain During command transfer this signal is in push pull mode I O CMOS 1...

Page 38: ...MOS 1 8V Standby also referred to as MISO SPI0_DO P46 SPI0 Master output Slave input O CMOS 1 8V Standby also referred to as MOSI SPI1_CS0 P54 SPI1 Master Chip Select 0 O CMOS 1 8V Standby See ESPI SP...

Page 39: ...RT0 ESPI_ALERT1 S43 S44 ESPI ALERT I OD CMOS 1 8V Standby This pin is used by eSPI slave to request service from eSPI master Alert is an open drain output from the slave This pin is optional for Singl...

Page 40: ...a single big list Below is an overview of all I2C busses and where to find them Name Pin Description Where to find I2C_LCD_DAT S140 DDC data line used for flat panel detection and control LVDS DSI eD...

Page 41: ...8V Runtime PU 470K on the Module Default use is GPIO3 alternative use is Camera 1 Reset active low through DTS GPIO4 HDA_RST P112 General purpose I O pin 4 I O CMOS 1 8V Runtime PU 470K on the Module...

Page 42: ...shake line for port 0 I CMOS 1 8V Runtime SER1_TX P134 Asynchronous serial data output port 1 O CMOS 1 8V Runtime SER1_RX P135 Asynchronous serial data input port 1 I CMOS 1 8V Runtime SER2_TX P136 As...

Page 43: ...V Runtime CAN1_RX P146 CAN port1 Receive input I CMOS 1 8V Runtime 4 4 4 Miscellaneous Name Pin Description I O Type I O Level Power Domain PU PD Comments TEST S157 Held low by Carrier to invoke Modul...

Page 44: ...p on module VIN_PWR_BAD S150 Power bad indication from Carrier board Module and Carrier power supplies other than Module and Carrier power supervisory circuits shall not be enabled while this signal i...

Page 45: ...r management I2C bus DATA I O OD CMOS 1 8V Runtime PU 2k2 On x86 systems these serve as SMB DATA Pulled up on module I2C_PM_CK P121 Power management I2C bus CLK O OD CMOS 1 8V Runtime PU 2k2 On x86 sy...

Page 46: ...OS 1 8Vsb Standby PU 10K Driven by OD on Carrier Pulled up on module Low on this pin allows non protected segments of Module boot device to be rewritten restored from an external USB Host on Module US...

Page 47: ...ND P2 P9 P12 P15 P18 P32 P38 P47 P50 P53 P59 P68 P79 P82 P85 P88 P91 P94 P97 P100 P103 P120 P133 P142 S3 S10 S16 S25 S34 S47 S61 S64 S67 S70 S73 S80 S83 S86 S89 S92 S101 S110 S119 S124 S130 S136 S143...

Page 48: ...ADLINK Technology Inc LEC iMX8M User s Guide Page 48 copyright 2021 ADLINK Technology Inc 4 5 SMARC pin to controller mapping...

Page 49: ...MIPI_VDDHA P12 GND P13 CSI1_RX2 In LVDS D PHY i MX8M MIPI_CSI2_D2_P MIPI_VDDHA P14 CSI1_RX2 In LVDS D PHY i MX8M MIPI_CSI2_D2_N MIPI_VDDHA P15 GND P16 CSI1_RX3 In LVDS D PHY i MX8M MIPI_CSI2_D3_P MIP...

Page 50: ...i MX8M ECSPI2_SS0 ALT0 NVCC_ECSPI P44 SPI0_CK Out SPI 1 8V i MX8M ECSPI2_SCLK ALT0 NVCC_ECSPI P45 SPI0_DIN In SPI 1 8V i MX8M ECSPI2_MISO ALT0 NVCC_ECSPI P46 SPI0_DO Out SPI 1 8V i MX8M ECSPI2_MOSI AL...

Page 51: ...NVCC_SAI1 P76 USB4_EN_OC In GPIO 3 3V USB Hub CYUSB3314 DS4_OVRCURR AVDD33 P77 PCIE_B_CKREQ N C N C P78 PCIE_A_CKREQ N C N C P79 GND P80 PCIE_C_REFCK Out N C N C P81 PCIE_C_REFCK Out N C N C P82 GND...

Page 52: ...GPIO1_IO05 ALT0 NVCC_GPIO1 P110 GPIO2 CAM0_RST Out PU 470K GPIO 1 8V i MX8M GPIO1_IO06 ALT0 NVCC_GPIO1 P111 GPIO3 CAM1_RST Out PU 470K GPIO 1 8V i MX8M GPIO1_IO06 ALT0 NVCC_GPIO1 P112 GPIO4 HDA_RST O...

Page 53: ...ER2_RTS N C N C P139 SER2_CTS N C N C P140 SER3_TX Out UART 1 8V i MX8M UART3_TXD ALT0 NVCC_UART P141 SER3_RX In UART 1 8V i MX8M UART3_RXD ALT0 NVCC_UART P142 GND P143 CAN0_TX Out CAN MCP2517FD TXCAN...

Page 54: ...M MIPI_CSI1_D1_N MIPI_VDDHA S16 GND S17 GBE1_MDI0 Bi Dir GBE MDI I210 MDI_PLUS 0 S18 GBE1_MDI0 Bi Dir GBE MDI I210 MDI_MINUS 0 S19 GBE1_LINK100 Out GPIO 3 3V I210 LED0 VDD3P3 S20 GBE1_MDI1 Bi Dir GBE...

Page 55: ...I2C3 i MX8M I2C3_SDA ALT0 NVCC_I2C S50 HDA_SYNC I2S2_LRCK SAI 1 8V i MX8M SAI3_TXFS ALT0 NVCC_SAI3 S51 HDA_SDO I2S2_SDOUT SAI 1 8V i MX8M SAI3_TXD ALT0 NVCC_SAI3 S52 HDA_SDI I2S2_SDIN SAI 1 8V i MX8M...

Page 56: ...C N C S79 PCIE_C_RX SERDES_2_RX N C N C S80 GND S81 PCIE_C_TX SERDES_2_TX N C N C S82 PCIE_C_TX SERDES_2_TX N C N C S83 GND S84 PCIE_B_REFCK Out PCIe 9FGV0441AKILF DIF1 VDDDIG1p8 S85 PCIE_B_REFCK Out...

Page 57: ...12 LVDS1_0 eDP1_TX0 DSI1_D0 Out Serial 0R LVDS SN65DSI84 B_Y0N S113 eDP1_HPD DSI1_TE N C N C S114 LVDS1_1 eDP1_TX1 DSI1_D1 Out Serial 0R LVDS SN65DSI84 B_Y1P S115 LVDS1_1 eDP1_TX1 DSI1_D1 Out Serial 0...

Page 58: ...K Out Serial 0R LVDS SN65DSI84 A_CLKN S136 GND S137 LVDS0_3 eDP0_TX3 DSI0_D3 Out Serial 0R LVDS SN65DSI84 A_Y3P S138 LVDS0_3 eDP0_TX3 DSI0_D3 Out Serial 0R LVDS SN65DSI84 A_Y3N S139 I2C_LCD_CK Out PU...

Page 59: ...8V i MX8M SAI5_RXD0 ALT5 NVCC_SAI5 S153 CARRIER_STBY Out GPIO 1 8V BMC PB5 1V8SMC S154 CARRIER_PWR_ON Out GPIO 1 8V BMC PB6 1V8SMC S155 FORCE_RECOV In PU 10K GPIO 3 3V 74LVC1G04 2 VDD_3V3 S156 BATLOW...

Page 60: ...oftware Support 5 1 1 Uboot Yocto Goto https github com adlink Yocto source code and compiling instructions are available 5 1 2 Ubuntu Build instruction from source are available on Github 5 1 3 Andro...

Page 61: ...LEC iMX8M User s Guide SGET SMARC Rev 2 1 Page 61 copyright 2021 ADLINK Technology Inc...

Page 62: ...ADLINK Technology Inc LEC iMX8M User s Guide Page 62 copyright 2021 ADLINK Technology Inc 6 Mechanical...

Page 63: ...ge 63 copyright 2021 ADLINK Technology Inc 7 Thermal Solutions LEC IMX8M has to be cooled by a passive Heatsink Heat spreader optionally available for ordering HTS sIMX8M Heatspreader for LEC iMX8M TH...

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