ADLINK Technology PXIe-9834, User Manual, Page: 54 / 65

42 Operations
Leading
EDGE COMPUTING
to maximize signal quality. Moreover, signal wiring must be pre-
cisely deployed to minimize timing skew.
The PXIe-9834, based on PXI Express HW & SW specifications,
enables trigger and clock signals to be fully leveraged and benefits
from the routing architecture of the PXI Express chassis. The PXI
Express chassis provides additional timing and synchronization
capabilities for more accurate measurement and improved new
application management. Overall PXI Express chassis instrumen-
tation signals are as follows.
Figure reprinted courtesy of PXI Express Specification Tutorial.pdf
from PXI System Alliance website (www.pxisa.org).
Figure 3-17: PXIe Instrumentation Signals
In the PXIe chassis, a system timing slot distributes trigger signals
through PXI_STAR and PXIe differential star triggers. The 8-bit
parallel PXI Trigger Bus provides additional channels for transmit-
ting and receiving triggers between peripheral slots. The PXIe
chassis further provides 10MHz (PXI_CLK10) clock options dis-
tributed to each peripheral slot with minimal clock skew.
PXI
PXI Express
100 MHz
Differential CLK
10 MHz
CLK
PXI Trigger Bus (8 TTL Triggers)
Star
Trigger
Differential
Star Triggers
PXI Express System T
iming
Controller
PXI Express System Controller PXI Express Peripheral
Hybrid Peripheral
PXI Peripheral
SYNC100