ADLINK Technology PXIe-9834, User Manual, Page: 39 / 65

Operations 27
PXIe-9834
Figure 3-3: Linked List of PCI Address DMA Descriptors
3.3 Trigger Source
This section details PXIe-9834’s triggering operations.
Figure 3-4: Trigger Architecture
The PXIe-9834 requires a trigger to implement acquisition of data.
Configuration of triggers requires identification of trigger sources.
The PXIe-9834 supports internal software trigger, external digital
trigger, analog trigger from AI CH0 to CH3, PXI Trigger Bus [0..7],
Local Memory
( FIFO)
PCI Express Bus
First PCI Address
First Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
PCI Address
Dual Address
Transfer Size
Next Descriptor
MUX
Software Trigger
External Digital Trigger
Analog Trigger
PXI Trigger Bus
PXI_STAR
PXIe_DSTARB
Trigger
Decision
To internal FPGA
PXI Trigger Bus