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Operation Theorem
The end-limit signals can be used to generate the IRQ by setting the bit 0
of INT. factor in software function:
_8132_set_int_factor()
.
You can use either 'a' contact switch or 'b' contact switch by setting the dip
switch S1. The PCI-8132 is delivered from the factory with all bits of S1
set to OFF.
The signal status can be monitored by software function:
_8132_get_
io_status().
4.3.3 ORG
When the motion controller is operated at the home return mode, the ORG
signal is used to stop the control output signals (OUT and DIR).
There are three home return modes, you can select one of them by setting
“
home_mode
” argument in software function: set_home_config(). Note
that if home_mode=1 or 2, the ORG signal must be ON or latched during
the EZ signal is inserted (EZ=0). The logic polarity of the ORG signal,
level input or latched input mode are selectable by software function:
_8132_set_ home_config()
.
After setting the configuration of home return mode by
_8132_set
_home_config()
, a home_move() command can perform the home return
function.
The ORG signal can also generate IRQ signal by setting the bit 5 of
interrupt reason register (or INT. factor) in software function:
_8132_set_int_factor()
.
4.3.4 SVON and RDY
The SVON signals are controlled by software function:
_
8132
_
Set_SVON()
. The function set the logic of AP0 (SVON) of
PCL5023. The signal status of SVON pins can be monitored by software
function:
_8132_get_io_status()
.
RDY pins are dedicated for digital input use The status of this signal can
be monitored by software function get_io_status(). RDY pin is interfaced
with AP3 pin of PCL5023 through a photocoulpe. The RDY signal can
also generate IRQ signal by setting the bit 23 of INT. factor in software
function: set_int_factor(). Note that interrupt is generated when AP3
from high to low.
4.4 The Encoder Feedback Signals (EA, EB, EZ)
The PCI-8132 has a 28-bits binary up/down counter for managing the
present position for each axis. The counter counts signals input from EA
and EB pins.