ADLINK Technology NuPRO-A301, User Manual

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46 BIOS Setup
5.4 Advanced Chipset Features
DRAM Timing Selectable
Selects whether DRAM timing is controlled by the SPD (Serial
Presence Detect) EEPROM on the DRAM module. Setting to "By
SPD" enables DRAM timing to be determined automatically by
BIOS based on the configurations on the SPD. Selecting Manual
allows users to configure these fields manually.
SLP_S4# Assertion Width
This item allows you to set the SLP_S4# Assertion Width. Options:
4 to 5 sec., 3 to 4 sec., 2 to 3 sec., 1 to 2 sec.
System BIOS Cacheable
Selecting “Enabled” allows caching of the system BIOS ROM at
F0000h- FFFFFh, resulting in better system performance. How-
ever, if any program writes data to this memory area, a system
error may occur. The options are “Enabled”, and “Disabled”.
Video BIOS Cacheable
Selecting “Enabled” allows caching of the video BIOS, resulting in
better system performance. However, if any program writes to this
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Features
DRAM Timing Selectable
X CAS Latency Time
X DRAM RAS# To CAS# Delay
X DRAM RAS# Precharge
X Precharge dealy (tRAS)
X System Memory Frequency
SLP_S4# Assertion Width
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
** VGA Setting **
PEG/OnChip VGA Control
On-Chip Frame Buffer Size
DVMT Mode
DVMT/FIXED Memory Size
Boot Display
By SPD
Auto
Auto
Auto
Auto
By SPD
1 to 2 Sec.
Enabled
Disabled
Disabled
Auto
8MB
DVMT
128MB
Auto
Item Help
______________________________
Menu Level
¾
↑↓→←
Move Enter: Select +/-/PU/PD: Value F10: Save ESC: Exit F1: General Help
F5: Previous Values F6: Fail-safe defaults F7: Optimized Defaults