ADLINK Technology NuDAQ cPCI-7249R, User Manual, Page: 43 / 74

Operation Theory 29
72XX Series
User’s Manual
4.2 Timer/Counter Operation
4.2.1 Introduction
One 8254 programmable timer/counter chip is installed in the
7248/96 series. There are three counters in one 8254 chip and six
possible operation modes for each counter. The block diagram of
the timer/counter system is shown in Figure 4.2.
Figure 4-2: Timer/counter system of 7248/96 series.
Timers #1 and #2 of the 8254 chip are cascaded as a 32-bit pro-
grammable timer. In the software library, Timers #1 and #2 are
always set as mode 2 (rate generator).
In software library, counter #0 is used as an event counter that is,
interrupt on terminal count of 8254 mode 0. Please refer to chapter
5 for programming the timer/counter functions.
Event IRQ
Counter #0
2 MHz Clock
Timer #1
Timer IRQ
Timer #2
8254 Chip
C
G
C
G
C
G
O
O
O
'H'
'H'
'H'
Trigger
Edge
Control
P1C4