nanoX-EL User’s Guide
PICMG COM.0 R3.0
Page 40
Copyright © 2021 ADLINK Technology, Inc.
4.3.12
SMBus
Name
Pin #
Description
I/O
PU / PD
Comment
SMB_CK
B13
System Management Bus bidirectional clock line. Power
sourced through 3.3V standby rail and main power rails.
I/O OD
3.3VSB
PU 2.2K
3.3VSB
SMB_DAT#
B14
System Management Bus bidirectional data line. Power
sourced through 3.3V standby rail and main power rails.
I/O OD
3.3VSB
PU 2.2K
3.3VSB
SMB_ALERT#
B15
System Management Bus Alert – active low input can be
used to generate an SMI# (System Management
Interrupt) or to wake the system. Power sourced through
3.3V standby rail and main power rails.
I 3.3VSB
PU 10K
3.3VSB
Note: SMBus from EC is BOM option supported by project basis
4.3.13
I2C Bus
Name
Pin #
Description
I/O
PU / PD
Comment
I2C_CK
B33
General purpose I²C port clock output/input
I/O OD
3.3VSB
PU 2.2K
3.3VSB
Source SEMA BMC as default (chipset by BOM
option)
I2C_DAT
B34
General purpose I²C port data I/O line
I/O OD
3.3VSB
PU 2.2K
3.3VSB
Source SEMA BMC as default (chipset by BOM
option)
Note: I2C from 6th Gen Intel Atom® x6000E processor is BOM option supported by project basis
