Express-TL User’s Guide
PICMG COM.0 R3.0
Page 18
Copyright © 2022 ADLINK Technology, Inc.
3.
Block Diagram
Figure 1 – Module function diagram
AB
DDI 1 / USB4
DDI 2 / USB4
DDI 3
PEG Port
PCIe 16 -31
USB 3.0 Lane 3
USB 3.0 Lane 2
USB 3.0 Lane 1
USB 3.0 Lane 0
PCIe Lane 6-7
DP to VGA
eDP to LVDS
DDR4 SODIMM
3200 MT/s
eDP/LVDS
VGA
USB 2.0 Lane 0-7
SATA Port 0-3
Max. 2.5GbE
PCIe Lane 0-3
PCIe Lane 4-5
HDA
SPI
SMBus
I2C
8xGPIO/SDIO
2xUART/CAN
LPC/eSPI
eSPI to LPC
LM73
(board)
Embedded
Controller
1 x4, 2 x2, 4 x1
Intel® Xeon®
11
th
Gen Intel® Core™/Celeron®
Processor
(Tiger Lake-H)
DDI B
(eDP 4lane
s)
eSPI
2 MIPI-CSI
1 PCIe Gen4 x4
TCP 0
Mobile Intel
Next Series Chipset
RM590E/QM580E/HM570E
SATA 6Gb/s
1 PCIe Gen3
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
eSPI
USB 3.2 Gen2 x1
USB 3.2 Gen2 x1
eDP x4
DDR4 SODIMM
3200 MT/s
ECC, non-ECC dependent on CPU/chipset config.
DMI (x8, Gen3)
16 PCIe
Gen4
LAN Controller
Intel I225
TSN dependent on controller SKU
4 PCIe Gen3
2 PCIe Gen3
2 x1
2 PCIe Gen3
2 x1
BIOS
Flash
BIOS
Flash
TPM 2.0
HSUART
1 x16 or 2 x8
or 1 x8 + 2 x4
DDR4 SODIMM
up to 3200 MT/s
DDR4 SODIMM
up to 3200 MT/s
BGA SSD
build option
x2
2 PCIe Gen3
3
rd
,4
th
socket dependent on SKU
1 x4 (Lane 4-7)
1 x4 (Lane 4-7)
DB30 x86
Connector
Fan
Connector
TCP 1
TCP 2
