cExpress-TL User’s Guide
PICMG COM.0 R3.0
Page 13
Copyright © 2021 ADLINK Technology, Inc.
2.2.1
Display Interface Support
LVDS
: Single/dual channel 18/24-bit LVDS through eDP to LVDS IC, supports DE mode and Hsync/Vsync mode.
Max. resolution 1920x1200@60Hz in dual mode. Pixel clock frequency up to 112 MHz. VESA and JEIDA panel data formats supported.
eDP
: eDP 1.4b up to 4 lane support, in place of LVDS (BOM option), up to 4096x2304@60Hz bpp with DSC
DDI x3
: Digital Display Ports (DDI) support DisplayPort 1.4a, HDMI 2.0b or DVI
VGA
: VGA BOM option support in place of DDI 3; max. resolution 1920x1200@60Hz
2.3.
Audio
Intel® HD Audio integrated
Located on carrier Express-BASE6 (ALC886 standard support)
2.4.
Expansion Busses
5 PCI Express x1 Gen3: Lanes 0,1,2,3 (configurable to 4 x1, 2 x2, 1 x4, 2 x1 + 1 x2, 1 x2 + 2 x1) and Lane 4 (x1 only)
A PCIe switch is HW BOM option by project basis to offer more x1 lanes via Lanes 5,6,7
1 PCI Express x4 Gen4: Lanes 16, 17, 18, 19 (x4 only), Gen4 support dependent on carrier design
Other: SMBus (system), I2C (user), LPC bus (via eSPI to LPC bridge IC)
