Active Technologies AT-1212 User Manual Download

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AT-1212 User Guide and Specifications - 36 -

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Filter Options

If necessary, images and sample clock feed-through can be largely removed using a low-pass filter;
Active Technologies suggests the following filters depending on the application and the user needs:



Mini Circuit RLP-470+



Mini Circuit

SBPL-467 (Maximally Flat Group Delay)



Mini Circuit

SCLF-550



Mini Circuit

SLP-550+



Mini Circuit

VLF-530



Mini Circuit

VLFX-500



Mini Circuit

SBPL-933+ (Maximally Flat Group Delay)

Calibration Service for AT-1212 (OPTIONAL)



Perform the calibration procedure.



Store the calibration parameters into the EEPROM module.



Verification of measurements according to specification.



Adjustment of performance if found outside specification.

Summary of Contents for AT-1212

Page 1: ...it High Speed Signal Generator Adapter Module for NI FlexRIO User Manual January 2013 Rev 1 3 Active Technologies S r l Via Bela Bartok 29 B 44124 Ferrara ITALY Tel 39 0532 91456 Fax 39 0532 970134 In...

Page 2: ...IGN 10 FPGA I O Interface 11 Clocking Scheme 12 Cables 13 LabView Interface 14 LabView Interface Host Side 17 Software Prerequisites 19 Example Code Review for AT 1212 adapter module 19 DACModuleContr...

Page 3: ...e and Specifications 3 www activetechnologies it Specifications 37 Configuration EEPROM Map 37 Electromagnetic Compatibility 37 CE Compliance 38 Appendix Installing EMI Controls 39 Installing PXI EMC...

Page 4: ...is document contains tutorial sections that demonstrate how to generate signals using a LabVIEW FPGA example VI and how to create and run your own LabVIEW project with the AT 1212R Note Before configu...

Page 5: ...minimize the potential for the product to cause interference to radio and television reception or to experience unacceptable performance degradation install and use this product in strict accordance w...

Page 6: ...s Available in your FPGA module hardwarekit and from the Start Menu Contains installation instructions for your NI FlexRIO system and specifications for your FPGA module NI Adapter Module User Guide a...

Page 7: ...ing down the module and connect signals only after the adapter module has been powered on by the NI FlexRIO FPGA module Device Front Panel Connector Signal Description TRIG IN SMA input connector for...

Page 8: ...ution Connections that exceed any of the maximum ratings of any connector on the AT 1212R can damage the device and the chassis Active Technologies is not liable for any damage resulting from such sig...

Page 9: ...n functionality of the user defined CLIP but it also allows the CLIP to communicate directly with circuitry external to the FPGA Adapter module socketed CLIP allows your IP to communicate directly wit...

Page 10: ...al from SMA connector The adapter module has a Clock Generator circuit that provides the 1 25 GHz clock to the DAC the clock generator source clock can be provided by 25 MHz onboard TCXO or by PXI_e D...

Page 11: ...MS s datadac_in0_ch1 datadac_in2_ch1 datadac_in4_ch1 datadac_in6_ch1 Input 13 0 Data for DAC Port 1 CH1 The user needs to send data to the Clip Inputs at IO Module Clock rate 156 25 MHz the datadac_in...

Page 12: ...ternal TCXO oscillator 25 MHz or from the PXI Express backplane clock In software use the ClockSelection1212 vi to select from the different clock sources If the user selects Internal and From Oscilla...

Page 13: ...MHz FlexRIO Clock used on the LabView interface of the clip ReadWriteTablesTest vi IO Module Clock 156 25 MHz clock from FAM Cables Use any shielded 50 coaxial cable with an SMA plug end to connect t...

Page 14: ...dac_in1_ch0 datadac_in3_ch0 datadac_in5_ch0 datadac_in7_ch0 are internally serialized by 4 to obtain a data rate of 625MS s PORT 1 DATA CH1 The LabView interface of the CLIP reads data from the look u...

Page 15: ...FPGA DCM has locked IO Module trig_out It sets the Trigger Out value IO Module trig_in indicator It reads the Trigger In value Write MEM CH0 Write MEM CH1 If true it writes the data contained into Wri...

Page 16: ...mode the Increment is fixed at 16 and Start Stop Address represent the start end point of the look up tables DataI2c0 Datai2c5 Data transferred by I2C write transfer ReadDataI2c Data retrieved by I2C...

Page 17: ...DEBUG as true Input Parameters FPGA VI Reference IN FPGA reference RIO Device CLOCK SELECTION DAC Clock source selection INTERNAL CLOCK Clock Generator input source Error in Output Parameters FPGA DCM...

Page 18: ...look up tables reading see section above Input parameters NumSamples the waveform length in samples DDS ARB DDS false or Arbitrary true generation mode FSampleDAC DAC sampling rate FoutDDS DDS wavefor...

Page 19: ...2 Example Code Review for AT 1212 adapter module DACModuleControl Host exe Software requirements Labview 2012 Modulation Toolkit This LabView application gives the user full access to all the main 112...

Page 20: ...e from 0 to 8191 b phase and number of cycles related to the waveform output frequency c Waveform type and the standard deviation of the gaussian noise that it is possible to add to the waveform The u...

Page 21: ...Generator circuit It can be From Oscillator onboard TCXO or From FPGA Clock from PXIe Backplane DSTARA Timing board DDS mode waveform generation parameters When the FAM works in DDS mode the user shou...

Page 22: ...on select the DAC clock source It can be Internal from Clock Generator circuit or External from SMA connector 1 25GHz Internal Clock Source select the source clock for the Clock Generator circuit It c...

Page 23: ...6674T NI Timing board and to the DSTARA DSTARB clock global trigger routing Set the DDS frequency to 156 25 MHz and fill the Destination Terminal Array The Destination Terminal Array should contain al...

Page 24: ...xRIO Adapter Module Support software includes a variety of example projects to help get you started creating your LabVIEW FPGA application This section explains how to use an existing LabVIEW FPGA exa...

Page 25: ...other than the NI 7962R select the FPGA target by using RIO Device Menu Ring 5 On the front panel in the resource pull down menu select an AT 1212 resource that corresponds with the target configured...

Page 26: ...rm pull down menu and choose its parameters 13 Press the Apply button to update the Waveform Graph 14 Press the Load Waveform button to load the samples into the FAM 15 Press the RUN SELECTED CH butto...

Page 27: ...t New VI A blank VI opens 2 Add a Waveform Graph indicator in the front panel 3 Add the RIO Device control located on Modern I O palette 4 Add a STOP button located on Express Buttons Switches 5 Add a...

Page 28: ...DAC B Aligned connect to AND operator FPGA DCM Locked case structure The FPGA DCM Locked and DAC A Aligned DAC B Aligned monitor if the initialization stage has been correctly terminated 12 Add a Fra...

Page 29: ...ter in the stacked sequence we will load the generated samples into the channels module 16 Add a For Loop structure and wire 2 to the Loop count 17 Place the WriteTables1212 Host vi located on AT_HS_S...

Page 30: ...d frame place the StartGeneration1212 Host vi located on AT_HS_Signal_Generator 1212 Module folder Connect the Channel Cluster TRUE TRUE and SYNC False 23 Add a Frame After in the stacked sequence 24...

Page 31: ...Connect one end of an SMA cable to AO 1 on the front panel of the AT 1212 and the other end to the oscilloscope 50 input 3 Tap the unused inputs AO 0 A1 with a 50 load 4 Open the front panel of Genera...

Page 32: ...mputer dialog box select the Existing Target or Device option button and expand FPGA Target The target is displayed 3 Select your device and click OK The target and target properties are loaded into t...

Page 33: ...select DStarA Clock as clockin and 40 MHz Onboard Clock as clockin40m Click OK 11 Copy the Memory1 element in the FPGA Target 1212 and paste it in the FPGA Target you have just created 12 Right click...

Page 34: ...ow and right click to open the LabView palette Select the FPGA I O palette and add an I O node 18 Wire the datadac_in0_ch0 datadac_in7_ch0 and datadac_in0_ch1 datadac_in7_ch1 connectors as in the pict...

Page 35: ...he Memory1 2047 has been reached If true it puts the memory address to the initial value 0 24 Save the VI Running the Host VI 1 Connect one end of an SMA cable to AO 0 on the front panel of the AT 121...

Page 36: ...the user needs Mini Circuit RLP 470 Mini Circuit SBPL 467 Maximally Flat Group Delay Mini Circuit SCLF 550 Mini Circuit SLP 550 Mini Circuit VLF 530 Mini Circuit VLFX 500 Mini Circuit SBPL 933 Maximal...

Page 37: ...uct performance that are not covered by warranty Typical values cover the expected performance of units over ambient temperature ranges of 23 5 C with an 95 confidence level based on measurements take...

Page 38: ...irect method CEI EN 61000 4 3 Radiated RF electro magnetic field immunity test Level 10V m mod 1kHz AM 80 at 3m of distance frequency range 80 1000MHz Level 3V m mod 1kHz AM 80 at 3m of distance frequ...

Page 39: ...FPGA Module Installation Guide and Specifications Installing PXI EMC Filler Panels Complete the following instructions to install PXI EMC filler panels National Instruments part number 778700 01 in yo...

Page 40: ...te You must populate all slots with a module or a PXI EMC filler panel to ensure proper module cooling Do not over tighten screws 2 5 lb in maximum For additional information about the use of PXI EMC...

Page 41: ......

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