AcroPack Series XMCAP2022
XMC Carrier Board
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consists of 3 bits to identify the site on the carrier where the AcroPack
module is installed and 5 bits that are determined by host's Geographical
Address bits (A0-A2) and the SW1 switch settings on the carrier (A3,A4). The
CPLD will serialize the slot address and transmit the address to the AcroPack
module as requested by the AcroPack module. The processes of reading the
slot address is typically initiated by host software. See CARRIER ADDRESS
ASSIGNMENT in section 2 for details regarding slot address selection.
JTAG
A JTAG interface is provided for programming and debugging FPGAs on
AcroPack modules. It is intended to be used with a Xilinx Platform USB II
programming device. A bypass circuit is included that will detect a vacant
AcroPack site and close a switch to complete the JTAG chain. The slot address
CPLD is included first in the JTAG chain for factory programming. When two
AcroPack modules with Xilinx FPGAs are installed on the carrier the module in
slot A appears next in the chain followed by the module in slot B.
POWER SUPPLY FET SWITCHES
The +5V, +12V, and -12V power supplies to each AcroPack module are
individually switched by onboard FETs. When the AcroPack PRESENT* signal,
Pin 45 on the mini-PCIe connector, is seen to be grounded these supplies are
turned on to supply voltage to the AcroPack module(s).
WARNING: When installing
a commercial mini-PCIe module onto the
XMCAP2022 board be sure that pin 45 on the module's mini-PCIe connector
is not grounded or damage to the module may result.
