INDUSTRIAL I/O PACK SERIES
AVME9675A
VME64x bus 6U CARRIER BOARD
Acromag, Inc. Tel: 248-295-0310
- 40 -
http://www.acromag.com
- 40 -
https://www.acromag.com
4.6 IP Read and Write Cycle Timing
An IP read or write cycle is carried out via a VME64x bus A24 or A16 data
transfer. The data transfer starts when the VME64x bus Data Strobe 0
(DS0*) goes active and ends when the carrier board drives Data Transfer
Acknowledge (DTACK*) active back to the VME64x bus master. The carrier
board typically has a 450ns IP module data transfer cycle time.
A typical IP module data transfer cycle is described here, starting with DS0*
going active. DS0* is sampled on the rising edge of the system 16MHz clock
edge after it goes active. All operations are then synchronized to the IP
8MHz clock as required by the IP module specification. Thus, typically one
8MHz clock cycle later, an IP select line goes active (IOSEL*, IDSEL*,
MEMSEL*, or INTSEL*) and is held active for one clock cycle. With no IP wait
states, an active IP Acknowledge (ACK*) signal is driven by the IP on the next
rising edge of the 8MHz clock. The carrier board samples ACK* one clock
cycle later and then asserts DTACK* ending the VME64x bus data transfer.
Timing Diagram
CLK 16MHz
CLK 8MHz
DS0*
IOSEL*
ACK*
DTACK*
A Time-out error will result for the following condition if Auto Acknowledge
is disabled in the carrier status register.
If a select line (IOSEL*, IDSEL*, INTSEL*, or MEMSEL*) is driven active to an
IP module and the IP module does not return ACK* active, then DTACK* will
also not be generated by the carrier board. This will cause a bus transfer
time-out error and the VME64x bus system may need to be reset. In
