INDUSTRIAL I/O PACK SERIES
AVME9675A
VMEx64 bus 6U CARRIER BOARD
Acromag, Inc. Tel: 248-295-0310
- 39 -
http://www.acromag.com
- 39 -
https://ww.acromag.com
pending interrupts can be monitored and cleared via carrier registers
IP
Interrupt Pending
and IP Interrupt Clear Registers
.
•
Lastly, pending interrupts can be globally monitored and released to the
VME64x bus via the
Status Register
.
4.4 IP Logic Interface
The IP logic interface is also implemented within the carrier board’s
FPGA.
The carrier board implements ANSI/VITA 4 1995 for 8 MHz operation only.
Industrial I/O Pack logic interface specification includes four IP logic
interfaces on an AVME9670. The VME64x bus address and data lines are
linked to the address and data of the IP logic interface. This link is
implemented and controlled by the carrier board’s FPGA.
The VME64x bus to IP logic interface link allows a VME64x bus master to :
•
Access up to 32 ID Space bytes for IP module identification (ID ROM
Data Format I) via D08(O) data transfers using VME64x bus A16 short
address space.
•
Access up to 128 I/O Space bytes of IP data via D16/D08(EO) data
transfers using VME64x bus A16 short address space.
•
Access up to 8Mbytes of IP data mapped to Memory Space via D16 or
D08(EO) transfers using VME64x bus A24 standard address space.
•
Respond to two IP module interrupt requests per IP with software
programmable VME64x bus interrupt levels.
4.5 Carrier Board Clock Circuitry
The VME64x bus 16MHz system clock is divided down by U10 (CDC3030D)
to obtain the IP module 8MHz clock signals. Separate IP clocks are driven to
each IP module. All clock lines include series damping resistors to reduce
clock overshoot and undershoot, and similar length PC board trace lengths
are employed to minimize clock skew between the IP modules.
