AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 16 - http://www.acromag.com
- 16 -
https://www.acromag.com
Plug-and-Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers and the Interrupt Register which must be read to
determine the base address assigned to the board and the interrupt request
that goes active on a board interrupt request.
Table 3.1 PCI Configuration
Registers
Address
Offset
D31 D24 D23 D16 D15 D8 D7 D0
0x00
Device ID
0x0354
Vendor ID
0x13A8
0x04
Status
Command
0x08
Class Code=0x070002
Rev ID=
Current REV
0x0C
BIST
Header
Latency
Cache
0x10
Memory Base Address for Memory Accesses
to PCIe interrupt and I/O registers
16K Space
(BAR0)
0x14-
0x28
Not Used
0x2C
Subsystem ID
0x0000
Subsystem Vendor ID
0x0000
0x30
Not Used
0x34-
0x38
Reserved
0x3C
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 16K byte block of memory (BAR0), to access UART
and device configuration registers. Only 8K is used, as the upper 8K is for a
second 'slave' UART' connected to the master, which does not exist on the
AP512 module.
