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Speedster7t GDDR6 User
Guide (UG091)

Speedster FPGAs

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Summary of Contents for Speedster7t GDDR6

Page 1: ...www achronix com Speedster7t GDDR6 User Guide UG091 Speedster FPGAs ...

Page 2: ...t is believed to be accurate and reliable However Achronix Semiconductor Corporation does not give any representations or warranties as to the completeness or accuracy of such information and shall have no liability for the use of the information contained herein Achronix Semiconductor Corporation reserves the right to make changes to this document and the information contained herein at any time ...

Page 3: ...of Operation 13 By 16 Mode 14 By 8 Clamshell Mode 14 Chapter 3 GDDR6 PHY Architecture 15 PHY Overview 15 PHY Features 16 PHY Architecture 17 Command Address Block 17 DQ Block 17 CA PLL 17 DQ PLL 17 Chapter 4 GDDR6 Clock and Reset Architecture 19 Chapter 5 GDDR6 Interface Connectivity 22 Connectivity to the Peripheral NoC 22 Connectivity Through the Beachfront 26 Chapter 6 GDDR6 Core and Interface ...

Page 4: ...Speedster7t GDDR6 User Guide UG091 www achronix com 4 Step 4 36 Step 5 37 Step 6 38 Revision History 39 ...

Page 5: ...Speedster7t GDDR6 User Guide UG091 www achronix com 5 ...

Page 6: ...M Standard JESD250 Data Rate Supports 12 Gbps 14 Gbps and 16 Gbps data transfer rate per pin delivering up to 512 Gbps per subsystem interface As a result the Speedster7t with eight GDDR6 subsystems can deliver a total bandwidth of 4 Tbps for the entire device Memory Interface The GDDR6 subsystem consists of two separate channels each providing a 16 bit interface Hence each subsystem provides a 32...

Page 7: ... that connect with the peripheral NoC over the FPGA fabric The GDDR6 subsystems can interface with the FPGA core in two ways NoC Interface By using the network hierarchy that allows high speed data flow between FPGA and peripheral interfaces Beachfront direct to fabric Interface By using the beachfront interface that connects the memory controller directly to the core All the eight GDDR6 subsystem...

Page 8: ...rview The GDDR6 subsystem provides a simple interface between off chip GDDR6 memory component and the user logic mapped to the FPGA core This memory subsystem comprises the PHY IP the controller IP clock and reset block APB interfaces and AXI4 interfaces to connect to the NoC and fabric Below is a block diagram of the GDDR6 subsystem ...

Page 9: ... The controller IP uses the available AXI interfaces to either talk directly to the fabric or connect to it through the NoC interface On the other side the controller is connected to the GDDR6 PHY via the DFI4 0 interface The controller has some sub modules such as read modify write reorder and the multi port front end cores The memory controller performs writes and reads to from the memory and ar...

Page 10: ...interface operates at 250 MHz and enables the user to configure the GDDR6 subsystem registers The subsystem registers are configurable through the APB slave interface where the master can be from the fabric or FPGA configuration unit FCU through the NoC The FCU configures the subsystem registers during boot up and the user can configure the registers from the fabric during user mode Supported Freq...

Page 11: ...emory throughput Controller Features The following table provides a list of important GDDR6 memory controller features Table 2 GDDR6 Controller Features Feature Description Maximum frequency The controller supports GDDR6 operation at up to 16 Gbps Controller clock rate Controller operates at half the rate of the command address clock Number of channels Two independent channels Individual channels ...

Page 12: ...ports GDDR6 error detection code on the data bus for both read and write transfers The memory device provides a checksum CRC per byte lane for any read or write data transfer to allow the controller to determine if the data transfer was completed correctly Error interrupt Mask able interrupt outputs for all detected error conditions with corresponding CSR read and clear on write registers Error re...

Page 13: ...emory interface and memory devices It consists of different pattern generators to support standalone testing during board bring up Memory Test Analyzer Core The memory test analyzer can compare the expected data with the read data and provide a status to the user It can also be used to capture memory test signals of interest Memory Controller Core This queue based high performance interface helps ...

Page 14: ...own below Figure 4 Dual Controller 16 Mode Block Diagram By 8 Clamshell Mode The controller can also be configured in 8 mode clamshell mode to talk to two memory devices Clamshell mode provides a way to double the density of the system by sharing the same command address bus between two devices in the system A block diagram of the configuration in a clamshell arrangement is shown here Figure 5 Dua...

Page 15: ...ntroller It supports a maximum data rate of 16 Gbps and is targeted for systems that require low latency and high bandwidth memory solutions The PHY consists of two independent 16 bit channels each composed of a modular command address block CA and two data byte DQ0 and DQ1 blocks The figure below shows the PHY interfacing with the off chip GDDR memory on one side and the memory controller on the ...

Page 16: ...BI Supports CABI where each controller has a bit to enable CABI CA format Double data rate DDR where data is latched on both edges of the clock CA serialization ratio 4 1 corresponds to command address clock CK to PHY clock PCLK frequency ratio of 2 1 CA driver impedance RON 40 48 60Ω CA termination 60 120 240Ω Data bus inversion DBI Supports DBI where each DQ byte has a bit for DBI DQ format DDR ...

Page 17: ...l signals in the PCLK domain Data is received from the DRAM with reference to WCK and passed on to controller in PCLK domain Per DQ eye timing adjustment for both transmit and receive paths Read write eye training and calibration such as WCK to CK Per pin internal V generation and calibration REF Registers for debug and control CA PLL The CA PLL block handles high speed clock CK CKN generation usi...

Page 18: ...Speedster7t GDDR6 User Guide UG091 www achronix com 18 Figure 7 High Level PHY I O Block Diagram ...

Page 19: ...PCNTL block is implemented in the subsystem which has the APB slave address decoding and subsystem CSR registers IPCNTL block operates off the CSR clock The diagram below shows the clock and reset block Figure 8 Clock and Reset Architecture of GDDR6 subsystem The global PLLs in the FPGA generate the 32 bit wide global clock gddr6_glb_clk and the reset block generates the global resets The clock an...

Page 20: ...de UG091 www achronix com 20 Figure 9 External Clock to South PLLs Driving the GDDR East West Subsystems on the AC7t1500 device Figure 10 External Clock to North PLLs Driving the GDDR East West Subsystems on the AC7t1500 device ...

Page 21: ...www achronix com 21 Figure 11 South PLLs Driving Some of the GDDR East West Subsystems and the North PLLs on the AC7t1500 device Figure 12 North PLLs Driving Some of the GDDR East West Subsystems and the South PLLs on the AC7t1500 device ...

Page 22: ...ve Similarly the FPGA master logic can issue a transaction to it s local Network Access Point NAP which carries it to the east or west side of the FPGA core where it is presented to the NoC From then on the NoC carries data to the appropriate GDDR6 interface The responses follow the same path in reverse In addition the NoC provides a connection from the FPGA fabric and IP interfaces to the FPGA co...

Page 23: ...Data width of AXI4 interface AXI_SLAVE_ID_WIDTH 7 Width of awid wid bid arid rid ports AXI_CMD_FIFO_AWIDTH 3 Sets the depth of the read and write command FIFOs The depth is equal to 2 AXI_CMD_FIFO_AWIDTH AXI_ADDR_WIDTH 33 Width of the awaddr and araddr ports AXI_LEN_WIDTH 8 Width of the length port SDRAM_DSIZE 256 Size of SDRAM MAX_SN_WIDTH 8 Bit width of the number of slots to be allocated in the...

Page 24: ...y so that it is presented to the AXI4 interface in the proper order For writes the AXI core must present data to the memory controller in the order requested by the controller ADDR_MAP_SIG_BITS 10 Sets the number of significant bits that are used in the address value comparison typically set to 10 BURST_SIZE_WIDTH 13 Width of burst size AXI_READ_ONLY 0 When set disables write accesses through port...

Page 25: ...e figure below shows PCI Express master issues a transaction to the NoC which transmits it directly to the GDDR6 interface without involving any resources in the FPGA fabric at all Figure 14 Data Flow from the PCIe Interface to GDDR6 Subsystem Through the NoC ...

Page 26: ...e per controller per subsystem capable of running up to 500 MHz supporting data rates of up to 16 Gbps AXI4 512b is a 512 bit slave interface which is connected to fabric master AXI Asynchronous read and write clock The write clock is half of the read clock An asynchronous FIFO handles clock domain crossing and 512 bit AXI to 256 bit local data conversion The write clock is provided by one of the ...

Page 27: ...ta width of the AXI4 interface AXI_SLAVE_ID_WIDTH 7 Width of awid wid bid arid rid ports AXI_CMD_FIFO_AWIDTH 3 Sets the depth of the read and write command FIFOs The depth is equal to 2 AXI_CMD_FIFO_AWIDTH AXI_ADDR_WIDTH 33 Width of the awaddr and araddr ports AXI_LEN_WIDTH 8 Width of the length port SDRAM_DSIZE 256 Size of SDRAM MAX_SN_WIDTH 8 Bit width of the number of slots to be allocated in t...

Page 28: ...so that it is presented to the AXI4 interface in the proper order For writes the AXI core must present data to the memory controller in the order requested by the controller ADDR_MAP_SIG_BITS 10 This sets the number of significant bits that are used in the address value comparison typically set to 10 BURST_SIZE_WIDTH 13 Width of burst size AXI_READ_ONLY 0 When set disables write accesses through t...

Page 29: ...t 1 Read or write CRC error signal for the corresponding channels to indicate an error when there is a CRC mismatch gddr6_ _chan 0 1 _interrupt Output 3 Interrupt output signal from the controller to perform further actions based on the error condition gddr6_ _chan 0 1 _interrupt_or Output 1 ORed output of all the interrupt signals connected to the fabric where the user can take further decision o...

Page 30: ...indicates that the channel is signaling valid write address and control information gddr6_ _chan0 1_awready Output 1 Output signal that indicates write address ready This signal indicates that the slave is ready to accept an address and associated control signals gddr6_ _chan0 1_awqos Input 3 Input signal to set the QoS identifier sent on the write address channel for each write transaction gddr6_...

Page 31: ...a read transaction gddr6_ _chan0 2_arcache Input 4 This signal indicates how a read transaction is required to progress through a system gddr6_ _chan0 1_arprot Input 3 This signal is used to set the following protection attributes of a read transaction privilege security level and access type gddr6_ _chan0 1_arvalid Input 1 This signal indicates that the read address channel signals are valid gddr...

Page 32: ...ock enable input to GDDR6 memory gddr6_ _ c0 c1 _sd_ca Output 10 Command address inputs to GDDR6 memory gddr6_ _ c0 c1 _sd_cabi_n Output 1 Active low command address bus Inversion input to GDDR6 memory gddr6_ _ c0 c1 _sd_wck_ n p Output 2 Differential clock inputs for data bus gddr6_ _ c0 c1 _sd_dq inout 16 Bidirectional data input output to and from memory gddr6_ _ c0 c1 _sd_dbi_n inout 2 Active ...

Page 33: ...sired IP is configured via the IO Designer GUI interface the tool generates a bitstream for the entire IP interface which is independent of the bitstream generated for the core fabric The tool then integrates both these bitstreams into a single configurable bitstream targeting a Speedster7t device The following steps provide a brief description on creating a GDDR6 IP interface design Step 1 Create...

Page 34: ...external input clock source Then GPIO IP select the ball placement and desired frequency for the GPIO Once the selection is made the Layout Diagram highlights the chosen clock input The IP Problems window highlights any errors or warnings which occurred while configuring the GPIO Figure 18 GPIO IP Configuration in ACE I O Designer ...

Page 35: ...interface The GDDR6 IP requires a GDDR6 reference clock for the controller and PHY operations and if the GDDR6 subsystem uses the beachfront interface then the PLL output needs to supply the beachfront AXI clock As result the number of PLL clock outputs must match the number of required clock inputs for the GDDR6 subsystem with the appropriate frequencies Figure 19 PLL IP Configuration in ACE I O ...

Page 36: ...t instantiate NoC IP with the appropriate clock setting The global clock output of the PLL should drive the NoC interface Note Although all the eight GDDR6 subsystems support NoC interfaces only the middle two GDDR6 subsystems on the east and west sides support beachfront connectivity Figure 20 NoC IP Configuration in ACE I O Designer ...

Page 37: ...d on the clock outputs from the PLL As the Speedster7t 7t1500 FPGA has eight GDDR6 subsystems with a subset of them being connected directly to the fabric interface there is the option of enabling the fabric interfaces based on the placement of the GDDR6 IP If the user intends to build a design with multiple GDDR6 subsystems then the existing GDDR6 subsystem can be cloned by selecting the option i...

Page 38: ...he required clock frequency Once these checks are done click in the I O Designer window to generate Generate IO Design Files all the necessary files including the bitstream for the entire IO ring Clicking this icon also generates the necessary simulation models and placement files required for integrating with the core design This step completes the I O ring configuration The user can now switch t...

Page 39: ...Speedster7t GDDR6 User Guide UG091 www achronix com 39 Revision History Version Date Description 1 0 11 Oct 2019 Initial release Save Save Save Save Save ...

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