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Microcode Patch Level
Processor Microcode Patch Level.
CPUID
Processor ID number.
CPU Stepping
Processor stepping information.
Processor L1 Instruction Cache Processor first-level instruction cache size detected
during POST.
An Instruction: to speed up executable instruction fetch.
Processor L1 Data Cache
Processor first-level data cache size detected
during POST.
A Data Cache: to speed up data fetch and store.
Processor L2 Cache
Processor second-level cache size detected
during POST.
Total L3 Cache per Socket
Processor third-level cache size detected
during POST.
Summary of Contents for AT115 F1
Page 1: ...Gateway GT115 Service Guide PART NO PRINTED IN TAIWAN ...
Page 12: ...8 Main Board MB R7F0A 001 FSP FSP450 60EP 450W POWER SUPPLY PY 45008 001 Mylar 47 R7F0L 001 ...
Page 20: ...16 Appearance of System Front view Item Component 1 USB connectors 2 LED indicator panel ...
Page 66: ...62 Figure 300 03 ...