Acer 390 Series, Service Manual

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Major Chips Description 2-5
2.1.3 Terminal Functions
This section describes the PCI1250A terminal functions. The terminals are grouped in tables by
functionality such as PCI system function, power supply function, etc. for quick reference. The
terminal numbers are also listed for convenient reference.
Table 2-2 PCI1250 Terminal Functions
Name No. I/O Type Function
Power Supply Terminals
GND A01, D04, D08, D13,
17, H04, H17, N04,
N17, U04, U08, U13,
U17, I Device ground terminals
VCC D06, D11, D15, F04,
F17, 04, L17, R04,
R17, U06, U10, U15 I 3.3 V Power supply terminal for core logic.
VCCA K02, R03, W05 I Rail Power Input for PC Card A Interface. Indicates
Card A signaling environment.
VCCB B16, C10, F18 I Rail Power Input for PC Card B Interface. Indicates
Card A signaling environment.
VCCI V10 I Rail power Input for interrupt subsystem interface
and miscellaneous l/O. Indicates signaling level of
the following inputs and shared outputs: IRQSER,
PCGNT. PCREQ SUSPENCX, SPKROUT,
GPI01:0, IRQMUX7:0, INTA, INTB CLOCK. DATA,
LATCH, and RI_OUT
VCCP K20, P18, V15, W20 I Rail power input for PCI signaling.
VCCZ A04, D01 I Rail power input for the Zoom Video Interface
PCI System Terminals
PCLK J17 I PCI bus clock. Provides timing fot all transactions
on the PCI bus. All PCI signals are sampled at the
rising edge H PCLK.
PRST J19 I PCI reset When the PCI bus reset is asserted the
PRST signal causes the PCI 1 250A to 3-state all
output buffers and reset all internal registers. When
PRST is asserted, the device is completely
nonfunctional. After PRST is deasserted, the
PCI1250A is in its default state.
When the SUSPEND mode is enabled, the device
is protected from the PRST clearing the internal
registers. An outputs are 3-statea but the contents
of the registers are preserved
CLKRUN J18 O PCI clock run. This signal is used by the central
resource to request permission to stop the PCI
clock or to slow it down, and the PCI1250A
responds accordingly.