Manual PCI-IDIO-16
12
Chapter 4: Programming
The base or starting address is assigned by the computer system during installation and will fall on an
eight byte boundary.
The card’s read and write functions are as follows:
I/O Address
Read
Write
Base +0
FET Drive Outputs 0-7
FET Drive Outputs 0-7
Base +1
Isolated Inputs 0-7
Clear Interrupt
Base +2
Enable IRQ
Disable IRQ
Base+3
Activate Input Filters 0-15 Deactivate Input Filters 0-15
Base+4
FET Drive Outputs 8-15
FET Drive Outputs 8-15
Base+5
Isolated Inputs 8-15
Unused
Base+6
Interrupt Status
Unused
Base +7
Input Filter Status 0-7
Control Input Filters 0-7
Digital Inputs
Digital input states are read as a pair of bytes from the ports at Base A1 and +5. Each of the
eight bits within each byte corresponds to a particular digital input. A "1" signifies that the input is
energized and a "0" signifies that the input is de-energized.
Bit Position
D7
D6
D5
D4
D3
D2
D1
D0
Input Low Byte
IP7
IP6
IP5
IP4
IP3
IP2
IP1 IP0
Input High Byte
IP15 IP14 IP13 IP12 IP11
IP10 IP9 IP8
FILTERS:
Sometimes it is necessary to slow down the card's response to eliminate noise spikes on DC
inputs in industrial environments or to convert sinusoidal AC inputs. The 5 mSec filter can be enabled for
all inputs 0-15 by a software read from base a3 or disabled by a write of any value to base
a3. The filters for inputs 0-7 can be programmed individually by a write to base a7 when
the previous global enable command has not been given; a value of one in the corresponding bit location
activates the filter and a value of zero disables that filter. The status of filters 0-7 can be read back from
base a7.
INTERRUPTS:
The card supports interrupts. The interrupt level is assigned by the BIOS or plug-and-play
operating system. The assigned interrupt level can be viewed when PCIFind.EXE is run (see chapter 3).
The card’s interrupt capability makes it is unnecessary to continuously poll inputs (by reading at base
a1 and +5) to detect when an input state has changed. To enable interrupts read from base
a2. To disable interrupts, write any value to base a2. To clear an interrupt write any
value to base a1. The user must include the clear instruction in the interrupt service routine
software. For shared interrupt applications the card has an IRQ status byte that can be read from base
a6. Bits 0 and 1 set indicate interrupts are enabled, bit 2 set indicates an IRQ has been
generated, bits 3 thru 7 will always read 0.
