Abov MC97F60128, User Manual, Page: 346 / 382

346
MC97F60128 ABOV Semiconductor Co., Ltd.
13.11 Register Description for Reset Operation
RSTFR (Reset Flag Register) : E8H
7 6 5 4 3 2 1 0
PORF EXTRF WDTRF OCDRF LVRF
– –
FPRIRF
R/W R/W R/W R/W R/W
– –
R/W
Initial value : 80H
PORF Power-On Reset flag bit. The bit is reset by writing
‘0’ to this bit.
0 No detection
1 Detection
EXTRF External Reset (RESETB) flag bit. The bit is reset by writing
‘0’ to this bit or by Power-
On Reset.
0 No detection
1 Detection
WDTRF Watch Dog Reset flag bit. The bit is reset by writing
‘0’ to this bit or by Power-On Reset.
0 No detection
1 Detection
OCDRF On-Chip Debug Reset flag bit. The bit is reset by writing
‘0’ to this bit or by Power-On
Reset.
0 No detection
1 Detection
LVRF Low Voltage Reset flag bit. The bit is reset by writing
‘0’ to this bit or by
Power-On Reset.
0 No detection
1 Detection
FPRIRF Flash ROM Parity Fail Reset flag bit. This bit is set to
‘1’ by a reset of
flash ROM parity fail detection during the CPU fetches the next flash
ROM data. This bit is reset by writing
‘0’ to this bit or by Power-On Reset.
0 No detection
1 Detection
NOTE)
1. When the Power-On Reset occurs, the PORF bit is only set to
“1”, the other flag (WDTRF and
OCDRF) bits are all cleared to
“0”.
2. When the Power-On Reset occurs, the EXTRF bit is unknown, At that time, the EXTRF bit can
be set to
“1” when External Reset (RESETB) occurs.
3. When the Power-On Reset occurs, the LVRF bit is unknown, At that time, the LVRF bit can be
set to
“1” when LVR Reset occurs.
4. When a reset except the POR occurs, the corresponding flag bit is only set to
“1”, the other flag
bits are kept in the previous values.