Abov MC96F6432S Series, User Manual

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MC96F6432S ABOV Semiconductor Co., Ltd.
8 Memory
The MC96F6432S addresses two separate address memory stores:Program memory and Data memory. The logical
separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-
bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated
through the DPTR register.
MC96F6432S provides on-chip 32Kbytes of the ISP type flash program memory, which can be read and written to.
Internal data memory (IRAM) is 256bytes and it includes the stack area. External data memory (XRAM) is 768bytes
and it includes 27bytes of LCD display RAM.
8.1 Program Memory
A 16-bit program counter is capable of addressing up to 64Kbytes, but this device has just 32Kbytes program memory
space.
Figure 8-1shows the map of the lower part of the program memory. After reset, the CPU begins execution from
location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump
to that location, where it commences execution of the service routine. External interrupt 11, for example, is assigned to
location 000BH. If external interrupt 11 is going to be used, its service routine must begin at location 000BH. If the
interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt
service routine is short enough (as is often the case in control applications), it can reside entirely within that 8bytes
interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other
interrupts are in use.