205
MC96F6432S
ABOV Semiconductor Co., Ltd.
11.12.20.3
USIn I2C Slave Transmitter
To operate I2C in slave transmitter, follow the recommended steps below.
1.
If the main operating clock (SCLK) of the system is slower than that of SCLn, load value 0x00 into
USInSDHR to make SDAn change within one system clock period from the falling edge of SCLn. Note that
the hold time of SDAn is calculated by SDAH x period of SCLK where SDAH is multiple of number of SCLK
coming from USInSDHR. When the hold time of SDAn is longer than the period of SCLK, I2C (slave) cannot
transmit serial data properly.
2.
Enable I2C by setting USInMS[1:0]bits in USInCR1 , IICnIEbit in USInCR4 and USInEN bit in USInCR2.
This provides main clock to the peripheral.
3.
When a START condition is detected, I2C receives one byte of data and compares it with USInSLA[6:0] bits
in USInSAR. If the GCALLn bit in USInSAR is enabled, I2C compares the received data with value 0x00, the
general call address.
4.
If the received address does not equal to USInSLA[6:0] bits in USInSAR, I2C enters idle state ie, waits for
another START condition. Else if the address equals to USInSLA[6:0] bits and the ACKnEN bit is enabled,
I2C generates SSELn interrupt and the SCLn line is held LOW. Note that even if the address equals to
USInSLA[6:0] bits, when the ACKnEN bit is disabled, I2C enters idle state. When SSELn interrupt occurs,
load transmit data to USInDR and clear to
“0b” all interrupt source bits in USInST2 to release SCLn line.
5.
1-Byte of data is being transmitted.
6.
In this step, I2C generates TENDn interrupt and holds the SCLn line LOW regardless of the reception of ACK
signal from master. Slave can select one of the following cases.
1) No ACK signal is detected and I2C waits STOP or repeated START condition.
2) ACK signal from master is detected. Load data to transmit into USInDR.
After doing one of the actions above, clear to
“0b” all interrupt source bits in USInST2 to release SCLn line. In
case of 1) move to step 7 to terminate communication. In case of 2) move to step 5. In either case, a
repeated START condition can be detected. For that case, move step 4.
7.
This is the final step for slave transmitter function of I2C, handling STOP interrupt. The STOPCn bit indicates
that data transfer between master and slave is over. To clear USInST2, write
“0” to USInST2. After this, I2C
enters idle state.
Summary of Contents for MC96F6432S Series
Page 15: ...15 MC96F6432S ABOV Semiconductor Co Ltd 4 Package Diagram Figure 4 1 44 Pin MQFP Package...
Page 16: ...16 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 2 32 Pin LQFP Package...
Page 17: ...17 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 3 32 Pin SOP Package...
Page 18: ...18 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 4 28 Pin SOP Package...
Page 19: ...19 MC96F6432S ABOV Semiconductor Co Ltd Figure 4 5 28 Pin TSSOP Package...
