Abov MC96F6332D, User Manual

Page: 294 / 327

MC96F6432
294 June 22, 2018 Ver. 2.9
13.9 Register Map
Table 13-3 Reset Operation Register Map
Name Address Dir Default Description
RSTFR E8H R/W 80H Reset Flag Register
LVRCR D8H R/W 00H Low Voltage Reset Control Register
LVICR 86H R/W 00H Low Voltage Indicator Control Register
13.10 Reset Operation Register Description
The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR),
and low voltage indicator control register (LVICR).
13.11 Register Description for Reset Operation
RSTFR (Reset Flag Register) : E8H
7 6 5 4 3 2 1 0
PORF EXTRF WDTRF OCDRF LVRF
– – –
R/W R/W R/W R/W R/W
– – –
Initial value : 80H
PORF Power-On Reset flag bit. The bit is reset by writing
‘0’ to this bit.
0 No detection
1 Detection
EXTRF External Reset (RESETB) flag bit. The bit is reset by writing
‘0’ to this bit
or by Power-On Reset.
0 No detection
1 Detection
WDTRF Watch Dog Reset flag bit. The bit is reset by writing
‘0’ to this bit or by
Power-On Reset.
0 No detection
1 Detection
OCDRF On-Chip Debug Reset flag bit. The bit is reset by writing
‘0’ to this bit or by
Power-On Reset.
0 No detection
1 Detection
LVRF Low Voltage Reset flag bit. The bit is reset by writing
‘0’ to this bit or by
Power-On Reset.
0 No detection
1 Detection
NOTES) 1. When the Power-On Reset occurs, the PORF bit is only set to
“1”, the other flag (WDTRF and
OCDRF) bits are all cleared to
“0”.
2. When the Power-On Reset occurs, the EXTRF bit is unknown, At that time, the EXTRF bit can be set
to
“1” when External Reset (RESETB) occurs.
3. When the Power-On Reset occurs, the LVRF bit is unknown, At that time, the LVRF bit can be set to
“1” when LVR Reset occurs.
4. When a reset except the POR occurs, the corresponding flag bit is only set to
“1”, the other flag bits
are kept in the previous values.