MC96F6432
288
June 22, 2018 Ver. 2.9
13.4 RESET Noise Canceller
The Figure 13.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation
value of about 2us
(@V
DD
=5V) to the low input of system reset.
Figure 13.2 Reset noise canceller timer diagram
13.5 Power on RESET
When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it
executes the device RESET function instead of the RESET IC or the RESET circuits.
Figure 13.3 Fast VDD Rising Time
Figure 13.4 Internal RESET Release Timing On Power-Up
VDD
nPOR
(Internal Signal)
Internal RESETB
Oscillation
BIT Starts
BIT Overflows
Slow VDD Rise Time, min. 0.05V/ms
V
POR
=1.4V (Typ)
VDD
nPOR
(Internal Signal)
Internal RESETB
Oscillation
BIT Starts
BIT Overflows
Fast VDD Rise Time, max 30.0V/ms
t > T
RNC
t > T
RNC
t > T
RNC
t < T
RNC
t < T
RNC
A
A
’
Summary of Contents for MC96F6332D
Page 24: ...MC96F6432 24 June 22 2018 Ver 2 9 4 Package Diagram Figure 4 1 48 Pin LQFP 0707 Package...
Page 25: ...MC96F6432 June 22 2018 Ver 2 9 25 Figure 4 2 44 Pin MQFP Package...
Page 26: ...MC96F6432 26 June 22 2018 Ver 2 9 Figure 4 3 32 Pin LQFP Package...
Page 27: ...MC96F6432 June 22 2018 Ver 2 9 27 Figure 4 4 32 Pin SOP Package...
Page 28: ...MC96F6432 28 June 22 2018 Ver 2 9 Figure 4 5 28 Pin SOP Package...
