Abov A96A148, User Manual, Page: 89 / 278

A96G140/A96G148/A96A148 User’s manual 10. Watchdog timer
89
10.2 WDT block diagram
BIT Overflow
or
BIT Overflow/8
WDTCNT
Watchdog Timer
Counter Register
WDTDR
[8E
H
]
[8E
H
]
comparator
WDTCR
Watchdog Timer
Data Register
Clear
WDTCL WDTRSON
WDTIFR
Clear
WDTEN
INT_ACK
WDTIF
To Reset
Circuit
BIT Overflow
BIT Overflow/8
WDTCK
Figure 29. Watch Dog Timer Block Diagram
10.3 Register map
Table 12. Watchdog Timer Register Map
Name Address Direction Default Description
WDTCNT 8EH R 00H Watch Dog Timer Counter Register
WDTDR 8EH W FFH Watch Dog Timer Data Register
WDTCR 8DH R/W 00H Watch Dog Timer Control Register
10.4 Register description
WDTCNT (Watch Dog Timer Counter Register: Read Case): 8EH
7 6 5 4 3 2 1 0
WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0
R R R R R R R R
Initial value: 00H
WDTCNT[7:0] WDT Counter