PulseTime
Ondelay
Output 1
PulseTime
Ondelay
Output 2
PulseTime
Ondelay
Output 3
Input 17
Input 32
Input 1
Input 16
IEC09000612_2_en.vsd
³
1
³
1
³
1
³
1
&
&
&
&
&
&
ModeOutput1=Pulsed
³
1
ModeOutput2=Pulsed
³
1
ModeOutput3=Pulsed
t
t
t
Offdelay
t
t
t
t
Offdelay
t
Offdelay
t
IEC09000612 V2 EN
Figure 166:
Trip matrix internal logic
Output signals from TMAGGIO are typically connected to other logic blocks or
directly to output contacts in the IED. When used for direct tripping of the circuit
breaker(s) the pulse time delay shall be set to approximately 0.150 seconds in order to
obtain satisfactory minimum duration of the trip pulse to the circuit breaker trip coils.
13.3
Configurable logic blocks
13.3.1
Standard configurable logic blocks
13.3.1.1
Functionality
A number of logic blocks and timers are available for the user to adapt the
configuration to the specific application needs.
•
OR
function block. Each block has 6 inputs and two outputs where one is
inverted.
•
INVERTER
function blocks that inverts the input signal.
1MRK 504 135-UEN A
Section 13
Logic
377
Technical manual
Summary of Contents for ret650
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