abaco systems SBC347A-11330001, Hardware Reference Manual

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64 SBC347A 3U VPX Single Board Computer Publication No. 500-9300527837-000 Rev. A.0
6.11 BIT Control and Status Register (0x629)
6.12 NVRAM Memory Space Page Register (0x635)
Bits 2 to 0 of this register make up bits 18 to 16 of the NVRAM address bus when
the NVRAM is accessed.
6.13 AXIS Timestamp Registers (0x648 to 0x64D)
These can be used to read the 48-bit timestamp. Reading register 0 latches the
current timestamp value into registers 1 to 5, so register 0 must always be read
first.
Bits Read/Write Description Default
7 Read/Write HRESET request:
1 = Board reset requested
0 = Board reset not requested
0
6 and 5 Read/Write BIT run status:
00 = BIT not previously run
01 = Fast BIT performed
10 = Full BIT performed
11 = Fast Start performed
00b (sticky when reset using HRESET request)
4 Read/Write BIT pass/fail:
1 = BIT failed
0 = BIT passed
1 (sticky when reset using HRESET request)
3 Read/Write Fast BIT:
1 = Fast BIT enabled (via BIOS setting)
0 = Fast BIT disabled
0
2 Read/Write Fast Start:
1 = Fast Start enabled (via BIOS setting)
0 = Fast Start disabled
0
1 Read only Reserved 0
0 Read/Write BIT run:
1 = BIT has been run
0 = BIT not been run
0 (sticky when reset using HRESET request)
Bits Read/Write Description Default
7 to 3 Read only Reserved 00000
b
2 to 0 Read/Write 64 KByte page select 000
b
AXIS Timestamp Register Address Timestamp Value Bits Default
0 0x648 7 to 0 (least significant byte) N/A
1 0x649 15 to 8 N/A
2 0x64A 23 to 16 N/A
3 0x64B 31 to 24 N/A
4 0x64C 39 to 32 N/A
5 0x64D 47 to 40 (most significant byte) N/A