Samsung AlphaPC 164BX User Manual Download

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AlphaPC 164UX/BX Motherboard

Technical Reference Manual

Preliminary

Summary of Contents for AlphaPC 164BX

Page 1: ...AlphaPC 164UX BX Motherboard Technical Reference Manual Preliminary ...

Page 2: ... any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung and Samsung logo are trademarks of Samsung Electronics Co Ltd Alpha Digital Semiconductor are trademarks of Digital Equipment Corporation FaxBACK and Intel are registered trademarks of Intel Corporation GRAFOIL is a registered trademark of Union C...

Page 3: ...tem Configuration and Connectors 2 1 AlphaPC 164UX Jumper Configuration 2 3 2 2 CPU Speed Selection Option 1 2 3 4 2 5 2 3 Bcache Size Jumpers Option 14 15 2 5 2 4 Boot Option Jumper Option 11 2 5 2 5 AlphaPC 164UX Connector Pinouts 2 5 2 5 1 PCI Bus Connector Pinouts 2 5 2 5 2 ISA Expansion Bus Connector Pinouts 2 8 2 5 3 SDRAM DIMM Connector Pinouts 2 9 2 5 4 EIDE Drive Bus Connector Pinouts 2 1...

Page 4: ...1 21174 Chip Overview 3 3 3 2 2 Main Memory Interface 3 4 3 2 3 PCI Devices 3 4 3 2 4 System IO SIO Chip 3 6 3 2 5 Ethernet LAN Controller Chip 3 6 3 2 6 PCI Ultra SCSI Fast 20 I O Processor Chip 3 7 3 2 7 PCI Expansion Slots 3 8 3 3 ISA Bus Devices 3 8 3 3 1 Combination Controller 3 9 3 3 2 XD Bus Device 3 10 3 3 3 ISA Expansion Slots 3 10 3 3 4 ISA I O Address Map 3 10 3 4 Flash ROM Address Map ...

Page 5: ...ter HAE_MEM A 18 A 7 2 Memory Access Rules and Operation A 18 A 8 PCI Sparse I O Space A 23 A 8 1 Hardware Extension Register HAE_IO A 23 A 8 2 PCI Sparse I O Space Access Operation A 23 A 9 PCI Configuration Space A 26 A 10 PCI Special Interrupt Cycles A 31 A 11 Hardware Specific and Miscellaneous Register Space A 31 A 12 PCI to Physical Memory Address A 32 A 13 Direct Mapped Addressing A 37 A 14...

Page 6: ...vi B 4 Enclosure B 4 C Support Products and Documentation Index ...

Page 7: ...and DMA Read and Write Transactions A 9 A 5 System Address Map A 11 A 6 21174 CSR Space A 12 A 7 Byte Word PCI Space A 13 A 8 Dense Space Address Generation A 17 A 9 PCI Memory Sparse Space Address Generation Region 1 A 21 A 10 PCI Memory Sparse Space Address Generation Region 2 A 22 A 11 PCI Memory Sparse Space Address Generation Region 3 A 22 A 12 PCI Sparse I O Space Address Translation Region ...

Page 8: ...ED Connector Pinouts J17 2 16 3 1 ISA I O Address Map 3 10 3 2 AlphaPC 164UX System Interrupts 3 13 3 3 ISA Interrupts 3 14 5 1 Power Supply DC Current Requirements 5 1 5 2 AlphaPC 164UX Motherboard Environmental Requirements 5 2 A 1 Physical Address Map Byte Word Mode Disabled A 1 A 2 Physical Address Map Byte Word Mode Enabled A 2 A 3 21164 Byte Word Addressing A 14 A 4 21164 Byte Word Translati...

Page 9: ...re the same The following sections are about AlphaPC 164UX motherboard only Audience This manual is intended for system designers and others who use the AlphaPC 164UX motherboard to design or evaluate computer systems based on the Samsung Alpha 21164 microprocessor and the Digital Semiconductor 21174 core logic chip Scope This manual describes the features configuration functional operation and in...

Page 10: ... ARCS BIOS and gives instruction to begin the installation of Windows NT Chapter 5 Upgrading the AlphaPC 164UX describes how to upgrade the AlphaPC 164UX motherboard s DRAM memory and microprocessor speed Chapter 6 Troubleshooting describes information about trouble shooting hard ware and software during AlphaPC 164UX startup Chapter 7 Power and Environmental Requirements describes the AlphaPC 164...

Page 11: ...de contiguous and noncontiguous bits contained in angle brackets Multiple contiguous bits are indicated by a pair of numbers separated by a colon For example 9 7 5 2 0 specifies bits 9 8 7 5 2 1 and 0 Similarly single bits are frequently indicated with angle brackets For example 27 specifies bit 27 Bit Field Abbreviation Description RO read only Bits and fields specified as RO can be read but not ...

Page 12: ...see Addresses Otherwise the base is indicated by a sub script for example 1002 is a binary number Ranges and Extents Ranges are specified by a pair of numbers separated by two periods and are inclu sive For example a range of integers 0 4 includes the integers 0 1 2 3 and 4 Extents are specified by a pair of numbers in angle brackets separated by a colon and are inclusive Bit fields are often spec...

Page 13: ...s are quite different and must be carefully distinguished In particular only privileged software that is software running in kernel mode can trigger UNDEFINED operations Unprivileged software cannot trigger UNDE FINED operations However either privileged or unprivileged software can trigger UNPREDICTABLE results or occurrences UNPREDICTABLE results or occurrences do not disrupt the basic operation...

Page 14: ... current access mode does not have access They must also not halt or hang the system or any of its com ponents For example a security hole would exist if some UNPREDICTABLE result depended on the value of a register in another process on the contents of processor temporary registers left behind by some previ ously running process or on a sequence of actions of different pro cesses UNDEFINED Operat...

Page 15: ...logic chip The AlphaPC 164UX provides a single board hardware and software development platform for the design integration and analysis of supporting logic and subsystems The board also provides a platform for PCI I O device hardware and software devel opment 1 1 System Components and Features The AlphaPC 164UX is implemented in industry standard parts and uses a Samsung Alpha 21164 microprocessor...

Page 16: ...ol Bcache 128 Bit Data SDRAM DIMM Sockets Address Control X6 1 Dedicated 64 Bit PCI Slot 5 Dedicated 32 Bit PCI Slots 1 Dedicated ISA Slot Combination Controller Diskette Parallel Port 2 Serial Ports Control Pdata Pecc Address Commands Tag Data 12 128 16 36 and Address 2 4MB L3 Primary PCI Bus 168 Pin Unbuffered PCI to PCI Bridge Ethernet Controller SCSI Controller SROM Buffer KBD Controller Real ...

Page 17: ...eneric functions to allow its use in a wide range of systems 1 1 2 Memory Subsystem The synchronous dynamic random access memory SDRAM is contained in three banks of dual inline memory modules DIMMs Single or double sided DIMMs may be used Each DIMM is 72 bits wide with 64 data bits and 8 check bits with 100 MHz or faster speed Two DIMMs provide 32Mb to 512MB of memory while six DIMMs provide up t...

Page 18: ...64MB 64MB 64MB 64MB 64MB 128MB 128MB 32MB 32MB 32MB 32MB 128MB 128MB 64MB 64MB 416MB 128MB 128MB 64MB 64MB 16MB 16MB 448MB 128MB 128MB 64MB 64MB 32MB 32MB 512MB 128MB 128MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 256MB 256MB 544MB 128MB 128MB 128MB 128MB 16MB 16MB 256MB 256MB 16MB 16MB 576MB 128MB 128MB 128MB 128MB 32MB 32MB 256MB 256MB 16MB 16MB 16MB 16MB 256MB 256MB 32MB 32MB 608MB 256MB 256...

Page 19: ...2MB 32MB 32MB 32MB 256MB 256MB 64MB 64MB 672MB 256MB 256MB 64MB 64MB 16MB 16MB 704MB 256MB 256MB 64MB 64MB 32MB 32MB 768MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 64MB 64MB 64MB 64MB 256MB 256MB 128MB 128MB 800MB 256MB 256MB 128MB 128MB 16MB 16MB 832MB 256MB 256MB 128MB 128MB 32MB 32MB 896MB 256MB 256MB 128MB 128MB 64MB 64MB 1024MB 256MB 256MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256M...

Page 20: ...6 combination controller chip that provides A diskette controller Two universal asynchronous receiver transmitters UARTs with full modem control A bidirectional parallel port A mouse and keyboard controller Real Time Clock 1 1 6 Miscellaneous Logic The AlphaPC 164UX contains the following miscellaneous components Synthesizer for clocks A clock synthesizer TQ2061 provides a programmable clock sourc...

Page 21: ...NT This firmware initializes the system and enables you to install and boot the Windows NT operating system The ARCSBIOS firmware resides in the flash ROM on the AlphaPC 164UX motherboard Binary images of the ARCSBIOS firmware are included in the Firmware update diskette along with a license describing the terms for use and distribution 1 3 Hardware Design Support The full design database includin...

Page 22: ...ocations The AlphaPC 164UX uses jumpers to implement configuration parameters such as system speed and boot parameters These jumpers must be configured for the user s environment Onboard connectors are provided for the I O interfaces DIMMs and serial and parallel peripheral ports Figure 2 1 shows the board outlines and identifies the location of jumpers connec tors and major components Table 2 1 l...

Page 23: ... 1 AlphaPC 164UX Jumper Connector Location U5 U6 U7 U8 J24 J33 J22 J21 J7 J6 J5 J2 J13 J25 J12 J34 Pwr LED IDE LED SCSI LED Pwr Switch Reset Switch GND FOK 12 Blk wire Yellow wire Red wire J10 U3 U4 J18 J16 J15 J28 U55 J31 J23 J30 J29 J17 J36 J37 J35 ...

Page 24: ...gth 32 bit PCI slot U5 DIMM socket 2 J7 Full length 32 bit PCI slot U6 DIMM socket 3 J10 Full length ISA slot U7 DIMM socket 4 J12 Serial Port connector U8 DIMM socket 5 J13 Parallel port connector U55 Microprocessor socket 21164 Alpha J15 Ultra Fast and Wide SCSI Connector J16 Narrow SCSI connector J17 SCSI LED connector J18 Power connector J21 Full length 32 bit PCI slot J22 Full length 32 bit P...

Page 25: ...uency 300 MHz In In In In In In In Out In In 333 MHz 366 MHz Out In Bcache Size In In Out Out Option14 Option15 0MB 1MB 2MB 4MB Out In Out In 400 MHz Out Out In In In Out In In Out In 433 MHz 466 MHz In Out 500 MHz In Out Out In Out Out In In In Out 533 MHz 566 MHz Out In 600 MHz Out In In Out Out In Out Out In Out 633 MHz 666 MHz In Out 700 MHz In In Out Out In Out Out Out Out Out 733 MHz 766 MHz...

Page 26: ...ng production the other jumpers shown in Figure 2 2 0 1 are for other implementations Note The standard motherboard is manufactured with 128K X 18 or 256K X 18 data SSRAMs 2 4 Boot Option Jumper Option 11 The boot option jumper is located at J28 21 22 Option 11 The default position for this jumper is out Figure 2 2 This jumper selects the image to be loaded into mem ory from the system flash ROM W...

Page 27: ...8 INTD B9 PRSNT1 B10 B11 PRSNT2 B12 Gnd B13 Gnd B14 B15 Gnd B16 CLK B17 Gnd B18 REQ B19 Vdd B20 AD 31 B21 AD 29 B22 Gnd B23 AD 27 B24 AD 25 B25 3V B26 C BE 3 B27 AD 23 B28 Gnd B29 AD 21 B30 AD 19 B31 3V B32 AD 17 B33 C BE 2 B34 Gnd B35 IRDY B36 3V B37 DEVSEL B38 Gnd B39 LOCK B40 PERR B41 3V B42 SERR B43 3V B44 C BE 1 B45 AD 14 B46 Gnd B47 AD 12 B48 AD 10 B49 Gnd B50 Not used B51 Not used B52 AD 08...

Page 28: ... A94 B63 B64 Gnd B65 C BE 6 B66 C BE 4 B67 Gnd B68 D 63 B69 D 61 B70 Vdd B71 D 59 B72 D 57 B73 Gnd B74 D 55 B75 D 53 B76 Gnd B77 D 51 B78 D 49 B79 Vdd B80 D 47 B81 D 45 B82 Gnd B83 D 43 B84 D 41 B85 Gnd B86 D 39 B87 D 37 B88 Vdd B89 D 35 B90 D 33 B91 Gnd B92 B93 B94 Gnd Table 2 2 PCI Bus Connector Pinouts Sheet 3 of 3 Pin Signal Pin Signal Pin Signal Pin Signal ...

Page 29: ... 22 AEN 23 SMEMR 24 SA19 25 IOW 26 SA18 27 IOR 28 SA17 29 DACK3 30 SA16 31 DRQ3 32 SA15 33 DACK1 34 SA14 35 DRQ1 36 SA13 37 REFRESH 38 SA12 39 SYSCLK 40 SA11 41 IRQ7 42 SA10 43 IRQ6 44 SA9 45 IRQ5 46 SA8 47 IRQ4 48 SA7 49 IRQ3 50 SA6 51 DACK2 52 SA5 53 TC 54 SA4 55 BALE 56 SA3 57 Vdd 58 SA2 59 OSC 60 SA1 61 Gnd 62 SA0 63 MEMCS16 64 SBHE 65 IOCS16 66 LA23 67 IRQ10 68 LA22 69 IRQ11 70 LA21 71 IRQ12 ...

Page 30: ... A0 34 A2 35 A4 36 A6 37 A8 38 A10 39 A12 40 3 3V 41 3 3V 42 CK0 43 Gnd 44 NC 45 S2 46 DQMB2 47 DQMB3 48 NC 49 3 3V 50 NC 51 NC 52 CB2 53 CB3 54 Gnd 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 3 3V 60 DQ20 61 NC 62 NC 63 CKE1 64 Gnd 65 DQ21 66 DQ22 67 DQ23 68 Gnd 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 3 3V 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 Gnd 79 CK2 80 NC 81 NC 82 SDA 83 SCL 84 3 3V 85 Gnd 86 DQ32 87 DQ33 88...

Page 31: ...43 3 3V 144 DQ52 145 NC 146 NC 147 PD 148 Gnd 149 DQ53 150 DQ54 151 DQ55 152 Gnd 153 DQ56 154 DQ57 155 DQ58 156 DQ59 157 3 3V 158 DQ60 159 DQ61 160 DQ62 161 DQ63 162 Gnd 163 CK3 164 NC 165 SA0 166 SA1 167 SA2 168 3 3V Table 2 5 EIDE Drive Bus Connector Pinouts J24 Pin Signal Pin Signal Pin Signal Pin Signal 1 RESET 2 Gnd 3 IDE_D7 4 IDE_D8 5 IDE_D6 6 IDE_D9 7 IDE_D5 8 IDE_D10 9 IDE_D4 10 IDE_D11 11...

Page 32: ...in Signal Pin Signal Pin Signal 1 Gnd 2 DEN0 3 Gnd 4 NC 5 Gnd 6 DEN1 7 Gnd 8 INDEX 9 Gnd 10 MTR0 11 Gnd 12 DR1 13 Gnd 14 DR0 15 Gnd 16 MTR1 17 Gnd 18 DIR 19 Gnd 20 STEP 21 Gnd 22 WDATA 23 Gnd 24 WGATE 25 Gnd 26 TRK0 27 Gnd 28 WRTPRT 29 ID0 30 RDATA 31 Gnd 32 HDSEL 33 ID1 34 DSKCHG Table 2 7 Parallel Bus Connector Pinouts J13 Pin Signal Pin Signal Pin Signal Pin Signal 1 STB 2 PD0 3 PD1 4 PD2 5 PD3...

Page 33: ...ard mouse connector pinouts Table 2 8 COM1 COM2 Serial Line Connector Pinouts J12 COM1 Pin Top COM1 Signal COM2 Pin Bottom COM2 Signal 1 DCD1 1 DCD2 2 RxD1 2 RxD2 3 TxD1 3 TxD2 4 DTR1 4 DTR2 5 SG1 5 SG2 6 DSR1 6 DSR2 7 RTS1 7 RTS2 8 CTS1 8 CTS2 9 RI1 9 RI2 Table 2 9 Keyboard Mouse Connector Pinouts J25 Keyboard Pin Bottom Keyboard Signal Mouse Pin Top Mouse Signal 1 KBDATA 1 MSDATA 2 NC 2 NC 3 Gnd...

Page 34: ... 3 Gnd 4 5 V dc 5 Gnd 6 5 V dc 7 Gnd 8 P_DCOK 9 5 V SB 10 12 V dc 11 3 3 V dc 12 12 V dc 13 Gnd 14 PS_ON 15 Gnd 16 Gnd 17 Gnd 18 5 V dc 19 5 V dc 20 5 V dc Table 2 11 Narrow SCSI Bus Connector J16 Pin Signal Pin Signal Pin Signal Pin Signal 1 GND 2 SD0 3 GND 4 SD1 5 GND 6 SD2 7 GND 8 SD3 9 GND 10 SD4 11 GND 12 SD5 13 GND 14 SD6 15 GND 16 SD7 17 GND 18 SDPO 19 GND 20 GND 21 GND 22 BUS_PRES 23 GND 2...

Page 35: ...9 GND 10 GND 11 GND 12 GND 13 GND 14 GND 15 GND 16 GND 17 TERMPWR1 18 TERMPWR1 19 NC 20 GND 21 GND 22 GND 23 GND 24 GND 25 GND 26 GND 27 GND 28 GND 29 GND 30 GND 31 GND 32 GND 33 GND 34 GND 35 SD12 36 SD13 37 SD14 38 SD15 39 SDP1 40 SD0 41 SD1 42 SD2 43 SD3 44 SD4 45 SD5 46 SD6 47 SD7 48 SDP0 49 GND 50 BUS_PRES 51 TERMPWR1 52 TERMPWR1 53 NC 54 GND 55 SATN 56 GND 57 SBSY 58 SACK 59 SRST 60 SMSG 61 ...

Page 36: ...essor fan power connector pinouts Table 2 14 Speaker Connector Pinouts J23 Pin Signal Name 1 SPKR Speaker output 2 NC 3 VDD 4 GND Table 2 15 Microprocessor Fan Power Connector Pinouts J35 Pin Signal Name 1 12V 2 FAN_OK_L Fan connected 3 GND 2 5 15 Pin Power LED Connector Pinouts Table 2 16 shows the power LED connector pinouts Table 2 16 Power LED Connector Pinouts J31 Pin Signal Name 1 Powerpullu...

Page 37: ...ws the soft power switch connector pinouts 2 5 19 SCSI LED Connector Pinouts Table 2 20 shows the SCSI LED connector pinouts Table 2 17 IDE Drive LED Connector Pinouts J29 Pin Signal Name 1 ACTIVITY Hard drive active 2 ACTIVUTYPULLUP Table 2 18 Reset Switch Connector Pinouts J37 Pin Signal Name 1 GND 2 RSTSWITCH Reset system Table 2 19 Soft Power Switch Connector Pinouts J36 Pin Signal Name 1 GND ...

Page 38: ... the AlphaPC 164UX major functional components Bus timing and protocol information found in other data sheets and reference docu mentation is not duplicated See Appendix C for a list of supporting documents and order numbers Note For detailed descriptions of bus transactions chip logic and operation refer to the 21164 Alpha Microprocessor Hardware Reference Manual and the Digital Semiconductor 211...

Page 39: ...ipelined accesses can decrease the cache loop times by one CPU cycle The Bcache supports 64 byte transfers to and from memory 3 2 Digital Semiconductor 21174 Core Logic Chip The 21174 core logic chip provides a cost competitive solution for designers using the 21164 microprocessor to develop uniprocessor systems The chip provides a 128 bit memory interface and a PCI I O interface and includes the ...

Page 40: ...ry addressing and control and the PCI bus A three entry CPU instruction queue is implemented to capture commands should the memory or I O port be busy Provides control to the Data Switch chips to isolate the L3 cache from the main memory bus during private reads and writes 21164 pc164ux 1 2 addr_bus_req adr_cmd_par cack cmd 3 0 dack fill fill_error fill_id idle_bc int4_valid 3 0 sys_res 1 0 tag_ct...

Page 41: ... Switches provide the interface between the 21164 L3 cache pdata 127 0 pecc 15 0 and the memory 21174 mdata 127 mecc 15 0 The AlphaPC 164UX supports six168 pin unbuffered 72 bit SDRAM DIMM modules Quadword ECC is supported on the SDRAM and CPU buses Even parity is generated on the PCI bus The AlphaPC 164UX supports a maximum of 1536MB of main memory The mem ory is organized as three banks Table 1 ...

Page 42: ...es parity on address and data cycles Three physical address spaces are supported 32 bit memory space 32 bit I O space 256 byte per agent configuration space 21174 pc164ux 8 10 Primary PCI Bus Device IDSEL Select p64_ad24 p64_ad25 p64_ad26 p64_ad28 SIO Bridge 21052 21143 PCI64 Slot 0 J2 Secondary PCI Bus Primary Secondary 64 Slot 0 53C875 32 Slot 0 32 Slot 1 32 Slot 2 32 Slot 3 32 Slot 4 Bus p32_ad...

Page 43: ...lave interface Fast IDE interface Plug n Play Port for Motherboard Devices Enhanced 7 channel DMA controller that supports fast DMA transfers PCI Specification Revision 2 1 Compliant Functionality of One 82c54 Timer Two 82c59 Interrupt Controller Functions X Bus Peripheral Support I O Advanced Programmable Interrupt Controller IOAPIC Support Nonmaskable interrupt NMI control logic Universal Serial...

Page 44: ...tal Semiconductor 21143 PCI CardBus 10 100 Mb s Ethernet LAN Controller Data Sheet and the Digital Semiconductor 21143 PCI CardBus 10 100 Mb s Ethernet LAN Controller Hard ware Reference Manual 3 2 6 PCI Ultra SCSI Fast 20 I O Processor Chip Performs wide high speed SCSI bus transfers in single ended and differential mode up to 40 MB s synchronous Ultra SCSI Fast 20 transfers and 14 MB s asynchron...

Page 45: ... AlphaPC 164UX ISA bus implementation with peripheral devices and connectors One dedicated ISA expansion slots are provided System support features such as serial lines parallel port and diskette controller are embed ded on the module by means of an FDC37C666 combination controller chip Figure 3 4 AlphaPC 164UX ISA Bus Devices PCI Bus la 23 17 sd 15 0 PCI to ISA Bridge 82371SB sd 7 0 Combination C...

Page 46: ...tion logic requiring no external filter compo nents Supports the 2 88MB drive format and other standard diskette drives used with 5 25 inch and 3 5 inch media FDC data and control lines are brought out to a standard 34 pin connector J33 A ribbon cable interfaces the connector to one or two diskette drives Serial ports Two UARTs with full modem control compatible with NS16450 or PC16550 devices are...

Page 47: ...e next level of software When power is turned on address ranges 0 to 00 00FF FFFF and 0F FC00 0000 to 0F FFFF FFFF are enabled After the system has been initialized these two address ranges are disabled Byte mode is then enabled in the 21164 and 21174 Byte mode is the only way to access the flash ROM in address range 87 C000 0000 to 87 FFFF FFFF 21164 byte instructions LDBU and STB must be used to...

Page 48: ... should be used to read the interrupt request vector from the SIO However the AlphaPC 164UX system has more external interrupts than the SIO can handle They are sent to an external Shift Registers This Shift Registers takes these interrupts with parallel When the Shift Registers are clocked data is shifted toward the serial output and generates irqchain2 finally During reset irq 3 0 convey the sys...

Page 49: ...ot PCI to ISA Bridge SIO 21174 64 PCI Slot v3_slot0irq3 v3_slot1irqX slotNirqX scsiirq flash_ready_irq irq8 irq 1 12 irq 3 4 6 7 irq 3 7 9 12 14 15 irq 1 3 7 9 12 14 15 isairq irqchain2 procirqs 6 0 pc164ux 23 pc164ux 26 pc164ux 8 10 pc164ux 28 pc164ux 36 pc164ux 23 pc164ux 25 pc164ux 25 pc164ux 25 pc164ux 20 22 pc164ux 24 pc164ux 8 pc164ux 33 pc164ux 33 pc164ux 31 pc164ux 29 Shift Register Shift ...

Page 50: ...phaPC 164UX Usage irq 0 20 Corrected system error Corrected ECC error and sparse space reserved encod ings detected by the 21174 irq 1 21 PCI and ISA interrupts irq 2 22 Interprocessor and timer interrupts irq 3 23 Reserved pwr_fail_irq 30 Powerfail interrupt Reserved mchk_irq 31 System machine check interrupt SIO NMI and 21174 errors hlt_irq Halt Reserved ...

Page 51: ... Interrupts Interrupt Number Interrupt Source IRQ0 Internal timer IRQ1 Keyboard IRQ2 Interrupt from controller 2 IRQ3 COM2 IRQ4 COM1 IRQ5 Available IRQ6 Diskette floppy IRQ7 Parallel port IRQ81 Reserved IRQ9 Available IRQ10 Available IRQ11 Available IRQ12 Mouse IRQ13 Available IRQ14 IDE IRQ15 IDE ...

Page 52: ...ck frequencies from 300MHz to 800 MHz The clock is provided by using a TQ2061 The TQ2061 s output is used as the input clock for the 21164 Clock distribution Clock distribution includes the distribution of system clocks from the 21164 microprocessor to the system logic The AlphaPC 164UX clock distribution scheme is flexible enough to allow the majority of cycle time combinations to be supported Be...

Page 53: ...amclkcx2 buf_dramclkdx2 DIMM4 DIMM5 buf_dramclkex2 buf_dramclkfx2 82371SB Bridge pc164ux 28 v83_sysclk ISA Slots pc164lx 29 PCI 32 Slots pc164ux 20 22 PCI to PCI Bridge 21052 Clock Driver 163344 pc164ux 4 pc164ux 19 p64_clk0 p32_clk7 p32_clk6 p32_clk5 p32_clk 4 0 Arbiter SCSI Controller pc164ux 18 pc164ux 24 Arbiter pc164ux 18 p64_clk1 p64_clk2 p64_clk3 p64_clk4 p64_clk5 p64_clk6 Ethernet Controll...

Page 54: ...PCI ISA bridge the PCI PCI controller Ethernet Control ler DMA Hack and the PCI arbiter 3 7 Reset and Initialization An external reset switch can be connected to J37 pc164UX 35 The reset function initializes the 21164 microprocessor and the system logic The vccok signal provides a full system initialization equivalent to a power down and power up cycle When dc_ok signal is inserted to 21174 chip 2...

Page 55: ...er from a user supplied PC power sup ply The power supply must provide 12 V dc and 12 V dc 5 V dc 3 V dc and 5 V dc Vdd The dc power is supplied through power connector J18 pc164ux 34 as shown in Figure 3 8 Power is distributed to the board logic through dedicated power planes within the eight layer board structure ...

Page 56: ...tc srom multi i o data switch Spkr 3 3 V Pull Ups Fan 21164 pc164ux 1 2 J18 10 P J35 5 V Vcc 12 V 12 V 5 V 2 5V Gnd pc164ux 23 PCI64 Conn pc164ux 23 Power Connector pc164ux 34 3 3 V Voltage Regulator pc164ux 34 3 5 7 13 4 6 19 20 1 2 11 15 16 17 18 12 Integrated Circuits 21174 dimm dimm buffer flash sram arbiter Ethernet controller pc164ux 26 PCI32 Conn pc164ux 20 22 ...

Page 57: ...ing SDRAM Memory You can upgrade memory in the AlphaPC 164UX by adding more DIMMs or replac ing the ones that you have with a greater size Use the following general guidelines 1 Observe antistatic precautions Handle DIMMs only at the edges to prevent damage 2 Remove power from the system 3 Open levers and align the DIMM 4 Firmly push the module into the connector Ensure that the DIMM snaps into th...

Page 58: ... replacing the microprocessor chip also replace the thermal conducting GRAFOIL pad See Appendix B for information about the parts kit which includes the heat sink GRAFOIL pad two hex nuts heat sink clips 60 mm fan and four screws 4 2 2 Required Tools The following tools are required when replacing the microprocessor chip A TS30 manual nut torque driver or equivalent with the following attachments ...

Page 59: ...1164 Microprocessor Install the new microprocessor in location U55 by performing the following steps Note Install the heat sink only after the microprocessor has been assembled to the ZIF socket 1 Observe antistatic precautions 2 Lift the ZIF socket actuator handle to a full 90 angle 3 Ensure that all the pins on the microprocessor package are straight 4 The ZIF socket and microprocessor are keyed...

Page 60: ...FOIL pad 1 Perform a visual inspection of the package slug to ensure that it is free of contamination 2 Wearing clean gloves pick up the GRAFOIL pad Do not perform this with bare hands because skin oils can be transferred to the pad 3 Place the GRAFOIL pad on the gold plated slug surface and align it with the threaded studs Guard Fan Alpha 21164 FM 06013 AI4 Heat Sink with Fan Mounting Holes Nut H...

Page 61: ... for the second nut 6 If the sink chip fan clip is used properly install it by positioning it over the assembly and hooking its ends around the ZIF socket retainers c Attach the heat sink fan assembly 1 Place the fan assembly on top of the heat sink aligning the fan mounting holes with the corresponding threaded heat sink holes Align the fan so that the fan power sensor wires exit the fan closest ...

Page 62: ... sensor is connected to the motherboard connector J35 When the signal is generated the speaker generates a tone 5 2 Environmental Requirements The 21164 microprocessor is cooled by a small fan blowing directly into the chip s heat sink The AlphaPC 164UX motherboard is designed to run efficiently using only this fan Additional fans may be necessary depending upon cabinetry and the requirements of a...

Page 63: ...connectors the 1 0 region to the left of the second PCI slots the fourth shows the ATX I O shield dimensions 5 3 1 Board Dimensions The AlphaPC 164UX motherboard is an ATX size printed wiring board PWB with the following dimensions Length 30 48 cm 12 0 in 0 0005 in Width 24 38 cm 9 6 in 0 0005 in Height 6 86 cm 2 7 in The board can be used in certain desktop and deskside systems that have adequate...

Page 64: ...3 2 Board Measurements and Hole Locations Figure 5 1 shows the Board Measurements and Hole Locations for the AlphaPC 164UX Figure 5 1 Board measurement and Hole Position Diagram Board Measurements and Hole Locations 9 600 250 650 3 1 400 3 750 5 550 12 00 250 1 300 ...

Page 65: ...quirements Physical Parameters 5 3 3 Board Vertical Clearance Figure 5 2 shows the Board Vertical Clearance for the AlphaPC 164UX Figure 5 2 Board Vertical Clearance Diagram 0 5 1 0 1 0 0 5 1 5 2 5 VerticalClearance Requirements 1 5 ...

Page 66: ...mensions for the AlphaPC 164UX Figure 5 3 ATX I O Shield Dimensions 0 54 020 990 240 256 856 247 1 134 1 774 2 436 3 454 4 924 Standard 25 pin DSUB connector cutout with this center point Standard 9 pin DSUB connector cutouts with these center points Radius 490 on both circles Dimensions represent center of circles 640 1 60 150 6 250 ...

Page 67: ...tion is controlled by PYXIS_CTRL1 0 IOA_BEN Table A 1 shows system address mapping operations when IOA_BEN equals 0 byte word operation disabled Table A 1 Physical Address Map Byte Word Mode Disabled Sheet 1 of 2 21164 Address1 Size GB Selection 00 000 0000 01 FFFF FFFF 8 00 Main memory E 0000 0000 E FFFF FFFF 4 00 Dummy memory region 80 0000 0000 83 FFFF FFFF 16 00 PCI sparse memory region 0 512M...

Page 68: ...0 87 FFFF FFFF 1 25 Reserved Table A 2 Physical Address Map Byte Word Mode Enabled Sheet 1 of 2 21164 Address Size GB Selection 00 000 0000 01 FFFF FFFF 8 00 Main memory E 0000 0000 E FFFF FFFF 4 00 Dummy memory region 80 0000 0000 83 FFFF FFFF 16 00 PCI sparse memory region 0 512MB 84 0000 0000 84 FFFF FFFF 4 00 PCI sparse memory region 1 128MB 85 0000 0000 85 7FFF FFFF 2 00 PCI sparse memory reg...

Page 69: ...00 PCI memory space INT4 A8 0000 0000 A8 FFFF FFFF1 4 00 PCI memory space INT2 B8 0000 0000 B8 FFFF FFFF1 4 00 PCI memory space INT1 89 0000 0000 89 FFFF FFFF 4 00 PCI I O space INT8 99 0000 0000 99 FFFF FFFF1 4 00 PCI I O space INT4 A9 0000 0000 A9 FFFF FFFF1 4 00 PCI I O space INT2 B9 0000 0000 B9 FFFF FFFF1 4 00 PCI I O space INT1 8A 0000 0000 8A FFFF FFFF 4 00 PCI configuration space type 0 IN...

Page 70: ...CI configura tion space In addition to these three address spaces on the PCI the 21164 s non cached space is also used to generate PCI interrupt acknowledge and special cycles The 21164 has visibility to the complete address space It can access the cached memory region the CSR region the PCI memory region the PCI I O region and the configuration regions see Figure 1 1 The PCI devices have a restri...

Page 71: ...3 0 equals addr_h 33 0 Directly mapped by concatenating an offset to a portion of the PCI address Virtually through a scatter gather translation map The scatter gather map allows any 8KB page of PCI memory address region to be redirected to any 8KB cached memory page as shown in Figure 1 2 21164 Environment Main System Memory PCI Memory Space PCI Window PCI I O Space PCI Device PCI Configuration S...

Page 72: ...ry address addr_h 33 0 equals PCI address ad 33 0 Window 3 can be either DAC or SAC but not both If DAC ad 63 40 must be zero ad 39 32 must match the DAC register and ad 31 0 must hit in win dow 3 Windows 0 1 and 2 are SAC only 1 Dual address cycle PCI 64 bit address transfer requires that address bits 63 32 con tain a nonzero value 2 Single address cycle PCI 32 bit address transfer requires that ...

Page 73: ...e The system provides three PCI sparse space memory regions allowing 704MB of total sparse space memory The three regions are relocatable using the HAE_MEM CSR The simplest configuration allows for 704MB of contiguous memory space 512MB region which may be located in any naturally aligned 512MB seg ment of the PCI memory space Software programmers may find this region sufficient for their needs an...

Page 74: ...4 Address Space Configuration LJ 05397 AI4 21164 Memory Space Reserved PCI Memory Dense Space PCI Memory Sparse Space PCI Windows PCI I O Space Scatter Gather or Direct Translation Cached Memory PCI Memory Space PCI I O Space 21164 Programmed I O DMA Read Write ...

Page 75: ...00 0000 01 FFFF FFFF 02 0000 0000 7F FFFF FFFF 00XXX 80 0000 0000 PCI Memory Sparse Space 704MB Maximum Reserved 8GB Cached Memory PCI I O Sparse Space 64MB Byte Word PCI Space 16GB PCI Memory Dense Space 4GB PCI Configuration CIA CSRs Flash ROM 83 FFFF FFFF 0100X 84 0000 0000 86 FFFF FFFF 0111X 87 0000 0000 87 FFFF FFFF 8B FFFF FFFF 1000X 88 0000 0000 84 FFFF FFFF 01010 85 0000 0000 01011 85 8000...

Page 76: ...ce memory region 3 contains 64MB PCI I O sparse space memory region A contains 32MB and is not relocatable PCI I O sparse space memory region B contains 32MB and is relocatable by way of the HAE_IO register PCI dense memory space contains 4GB for 21164 noncached 21164 transac tions It is used for devices with access granularity greater or equal to a LW Read prefetching is allowed and thus read tra...

Page 77: ...Sparse Memory Space 64MB Region 3 0 0 0 0 0 0 0 0 0 0 0 2 3 6 7 1 0 0 0 Size 0 3 6 7 Size 3 6 7 0 0 0 X 0 35 35 35 0 0 30 1 0 31 2 1 0 34 33 32 38 39 PCI I O Address 24 2 1 1 0 PCI I O Sparse Space 32MB Region A Size 3 6 7 0 0 0 X 0 35 0 0 30 1 0 29 1 31 2 1 0 34 33 32 38 39 PCI I O Address 24 2 1 1 0 PCI I O Sparse Space 32MB Region B Size 3 6 7 0 0 0 X 0 35 0 0 30 1 29 1 1 31 2 1 0 34 33 32 38 3...

Page 78: ... divided into four regions memory I O configuration type 0 and configu ration type 1 as shown in Figure 1 7 31 2 1 0 34 33 32 38 39 Address 1 0 PCI Configuration Space Size 3 6 7 0 0 X 0 35 0 0 28 27 CSR Space 1 1 1 CPU Address 31 30 29 28 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Size GB 0 5 0 5 0 25 0 25 0 25 0 25 2 00 PCI Configuration Space PCI IACK Special Cycle 21174 Main CSRs Main Memor...

Page 79: ...tructions can also be packed to the same 32 byte block Byte word support is enabled when 21164 IPR register ICSR 17 equals 1 and when 21174 CSR register PYXIS_CTRL1 0 also equals 1 31 2 1 0 LJ 05399 AI4 36 37 35 34 33 32 38 39 PCI Memory Address 31 2 0 1 X 0 0 1 Size 0 0 PCI Memory Space 4GB 31 0 36 37 35 34 33 32 38 39 PCI I O Address 1 1 X 0 0 1 Size PCI I O Space 4GB 31 2 1 0 36 37 35 34 33 32 ...

Page 80: ...ng transactions have multiple data transfers on the PCI INT4 write transactions INT8 read and write transactions Table A 3 21164 Byte Word Addressing Instruction addr_h 38 37 int4_valid 3 2 1 0 LDQ 00 INT8 LDL 01 addr_h 3 2 Undefined LDWU 10 addr_h 3 1 Undefined LDBU 11 addr_h 3 0 STQ 00 INT4 Mask STL 01 INT4 Mask STW 10 addr_h 3 1 Undefined STB 11 addr_h 3 0 Table A 4 21164 Byte Word Translation ...

Page 81: ...e buffer in sparse space it cannot hand over the buffer to the common Windows NT operating system graphics code Higher bus bandwidth PCI bus burst transfers are not usable in sparse space except for a 2 longword burst for quadword write transactions Dense space is defined to allow both burst read and write transactions Efficient read write buffering In sparse space separate transactions use sepa r...

Page 82: ...refore this space cannot be used for devices that have read side effects Although a longword may be prefetched the prefetch buffer is not treated as a cache and so coherency is not an issue A quadword read transac tion is not atomic on the PCI that is the target device is at liberty to force a retry after the first longword of data is sent and then to allow another PCI device to take control of th...

Page 83: ...ddr_h 4 3 ad 2 differs for read and write transactions as follows For a read transaction ad 2 is zero that is the minimum read transaction resolution in noncached space is a quadword For a write transaction ad 2 equals addr_h 2 1 7 PCI Sparse Memory Space The system provides three regions of contiguous 21164 address space that maps to PCI sparse memory space The total 21164 range is from 80 0000 0...

Page 84: ...urpose leaving the remaining addr_h 31 7 signals to generate a PCI longword address 26 3 1 This loss of address bits has resulted in a 21164 22GB sparse 32 bit address space that maps to only 704MB of address space on the PCI The rules for accessing sparse space are as follows Sparse space supports all the byte encodings that may be generated in an Intel system to ensure compatibility with PCI dev...

Page 85: ... PCI space An important point to note is that signals addr_h 33 5 are directly available from the 21164 pins On read transactions the 21164 sends out addr_h 2 0 indirectly on the int4_valid pins Signals addr_h 2 0 are required to be zero Transactions with addr_h 2 0 not equal to zero will pro duce UNPREDICTABLE results Table A 5 shows the relation between int4_valid 3 0 and addr_h 4 3 for a sparse...

Page 86: ...se memory space ad 1 0 is always zero 4 Missing entries for example word size with 21164 address 11 enjoy UNPREDICTABLE results Table 1 6 PCI Memory Sparse Space Read Write Encodings Size Byte Offset addr_h 6 5 21164 Instruction Allowed ad 2 0 PCI Byte Enable1 Data In Register Byte Lanes 63 32 31 0 addr_h 4 3 00 A 7 2 003 1110 OOOX 01 A 7 00 1101 OOXO Byte 00 10 LDL STL A 7 00 1011 OXOO 11 A 7 00 ...

Page 87: ...1 9 PCI Memory Sparse Space Address Generation Region 1 Table 1 7 PCI Address Mapping 21164 Address Region ad 31 30 29 28 27 26 80 0000 0000 to 83 FFFF FFFF 1 HAE_MEM 31 HAE_MEM 30 HAE_MEM 29 CPU 33 CPU 32 CPU 31 84 0000 0000 to 84 FFFF FFFF 2 HAE_MEM 15 HAE_MEM 14 HAE_MEM 13 HAE_MEM 12 HAE_MEM 11 CPU 31 85 0000 0000 to 85 FFFF FFFF 3 HAE_MEM 7 HAE_MEM 6 HAE_MEM 5 HAE_MEM 4 HAE_MEM 3 HAE_MEM 2 SBZ...

Page 88: ...ration Region 3 SBZ PCI Address 4 3 Length in Bytes Byte Offset HAE_MEM CSR PCI QW Address LJ 04266 AI4 1 1 21164 Address 0 0 21164 int4_valid 31 02 01 00 34 33 05 04 03 02 00 39 38 35 06 07 08 31 15 03 32 31 27 26 16 10 00 11 0 0 SBZ PCI Address 4 3 Length in Bytes Byte Offset HAE_MEM CSR PCI QW Address LJ 04267 AI4 1 1 21164 Address 0 0 21164 int4_valid 31 02 01 00 34 33 05 04 03 02 00 39 38 35 ...

Page 89: ...the range 85 8000 0000 to 85 FFFF FFFF This space has characteristics similar to the PCI sparse memory space This 2GB 21164 address segment maps to two 32MB regions of PCI I O address space A read or write transaction to this space causes a PCI I O read or write command The high order PCI address bits are handled as follows Region A This region has addr_h 34 30 10110 and addresses the lower 32MB o...

Page 90: ...ble 1 8 PCI Sparse I O Space Read Write Encodings Size Byte Offset addr_h 6 5 21164 Instruction Allowed ad 2 0 PCI Byte Enable1 Data In Register Byte Lanes 63 32 31 0 addr_h 4 3 00 A 7 2 00 1110 OOOX 01 A 7 00 1101 OOXO Byte 00 10 LDL STL A 7 00 1011 OXOO 11 A 7 00 0111 XOOO 00 A 7 00 1100 OOXX Word3 01 01 LDL STL A 7 00 1001 OXXO 10 A 7 00 0011 XXOO 00 A 7 00 1000 OXXX Tribyte 10 01 LDL STL A 7 0...

Page 91: ...BZ PCI Address 4 3 Length in Bytes Byte Offset LJ 04268 AI4 1 1 21164 Address 0 0 21164 int4_valid 31 02 01 00 34 33 05 04 03 02 00 39 38 35 06 07 08 03 32 31 25 24 30 29 0 1 1 0 0 0 0 0 0 0 0 29 8 PCI Address 4 3 Length in Bytes Byte Offset HAE_IO CSR LJ04269A AI4 21164 Address 21164 int4_valid 31 02 01 00 34 33 05 04 03 02 00 39 38 35 06 07 08 31 24 03 32 31 25 24 25 30 29 SBZ 1 1 0 0 0 1 1 1 ...

Page 92: ...Type 0 These are targets on the primary 64 bit PCI bus These targets are selected by making CFG 1 0 0 Type 1 These are targets on the secondary 32 bit PCI bus that is behind a PCI to PCI bridge These targets are selected by making CFG 1 0 1 Note CFG 1 0 10 or 11 are reserved by the PCI specification Software must program the CFG register before running a configuration cycle Sparse address decoding...

Page 93: ...pe 0 PCI Configuration Address CPU Address Type 1 PCI Configuration Address 00 LJ04270A AI4 0 0 0 0 0 0 Bus Device Function Register 0 1 0 0 31 27 26 24 23 16 15 11 10 07 08 02 01 00 Byte Offset 31 11 10 07 08 02 01 00 IDSEL Function Register 0 0 31 24 16 15 07 02 CFG 1 0 00 LJ 05400 AI4 Byte Offset 01 08 10 11 23 31 07 02 00 01 08 10 11 31 24 16 15 07 02 00 01 08 10 11 23 27 26 IDSEL Function Reg...

Page 94: ...ed by the peripheral to select one of eight functional units Signals ad 31 11 are available to generate the IDSEL bits note that IDSEL bits behind a PCI to PCI bridge are determined from the device field encoding of a type 1 access The IDSEL pin of each device is connected to a unique PCI address bit from ad 31 11 The binary value of addr_h 20 16 is used to select which ad 31 11 is asserted as sho...

Page 95: ...n space Table 1 10 contains the PCI configuration space read write encodings Each PCI to PCI bridge can be configured via PCI configuration cycles on its primary PCI interface Configuration parameters in the PCI to PCI bridge will identify the bus number for its secondary PCI interface and a range of bus numbers that may exist hier 1 Byte enable set to 0 indicates that byte lane carries meaningful...

Page 96: ...e of bus numbers that may exist hierarchically behind its secondary PCI interface the bridge chip passes the PCI con figuration cycle on unmodified ad 1 0 01 It will be accepted by a bridge further downstream Figure 1 16 shows a typical PCI hierarchy This is only one example of how the 21174 can be used in a system design Figure 1 16 PCI Bus Hierarchy LJ 05401 AI4 SCSI SCSI SCSI Ethernet PCI to PC...

Page 97: ... the hexword with the following fields Bytes 0 and 1 contain the encoded message Bytes 2 and 3 are message dependent optional data fields A read of the same address range will result in an Interrupt Acknowledge cycle on the PCI and return the vector data provided by the PCI EISA bridge to the 21164 1 11 Hardware Specific and Miscellaneous Register Space These registers are located in the range 87 ...

Page 98: ...address can be direct direct mapped physical mapping with an address offset or scatter gather mapped virtual mapping These five address windows are referred to as the PCI target windows Window 4 maps directly using the Monster Window with dual address cycles DAC where ad 33 0 equals addr_h 33 0 The following three registers are associated with windows 3 0 Window base W_BASE register Window mask W_...

Page 99: ... hit occurs in any of the four windows that are enabled then the 21174 will respond to the PCI cycle by asserting the signal devsel The PCI target windows must be programmed so that their address ranges do not overlap otherwise the results are UNDEFINED 1 Only the incoming ad 31 n are compared with 31 n of the window base register as shown in Figure 1 18 If n 32 no comparison is performed Table A ...

Page 100: ...ers the base and limit address registers These regis ters accurately specify the address space that the bridge device will respond to2 and are programmed by the power on self test POST code The 21174 as a PCI host bridge device does not have base and limit registers3 but does respond to all the addresses defined by the window base register that is all addresses within a win dow Figure 1 17 shows h...

Page 101: ...39 32 must match the window DAC base register and ad 31 20 must also have a compare hit This scheme allows a naturally aligned 1MB 4GB PCI window to be placed any where in the first 1TB of a 64 bit PCI address When an address match occurs with a PCI target window the 21174 translates the 32 bit PCI address to addr_h 33 0 1 Dual address cycle DAC only issued if 63 32 are nonzero for a 64 bit addres...

Page 102: ...ndow 3 Only W_DAC 63 40 39 32 31 02 n n 1 20 19 PCI Address Target Window Hit Logic Wn_MASK Wn_BASE Compare Hit Logic LJ04273A AI4 31 n n 1 20 00000000 11111 DAC XXXXX 31 n n 1 20 Hit Window 3 Hit Window 2 Hit Window 1 Hit Window 0 Window 3 SG Bit Window Enable WENB Window 2 SG Bit Window 1 SG Bit Window 0 SG Bit ...

Page 103: ...ays zero Because the translated base is simply concatenated to the PCI address then the direct mapping is to a naturally aligned memory region For example a 4MB direct mapped window will map to any 4MB region in main memory that falls on a 4MB boundary for instance it is not possible to map a 4MB region to the main memory region 1MB 5MB Table A 13 lists direct mapped PCI target address translation...

Page 104: ...ace into an 8KB page of the 21164 address space This offers a number of advantages to software Performance ISA devices map to the lower 16MB of memory The Windows NT operating system currently copies data from here to user space The scatter gather map eliminates the need for this copy operation User I O buffers might not be physically contiguous or contained within a page With scatter gather mappi...

Page 105: ...BLE Figure 1 19 Scatter Gather PTE Format The size of the scatter gather map table is determined by the size of the PCI target window as defined by the window mask register shown in Table A 14 The number of entries in the table equals the window size divided by the page size 8KB The size of the table is simply the number of entries multiplied by 8 bytes The scatter gather map table address is obta...

Page 106: ... addresses as the TLB data as shown in Figure 1 20 1 Unused bits of the Translated Base Register must be zero for correct operation 0000 0001 1111 32KB Translated Base 33 15 ad 24 13 0000 0011 1111 64KB Translated Base 33 16 ad 25 13 0000 0111 1111 128KB Translated Base 33 17 ad 26 13 0000 1111 1111 256KB Translated Base 33 18 ad 27 13 0001 1111 1111 512KB Translated Base 33 19 ad 28 13 0011 1111 ...

Page 107: ... TLB entry to be replaced is determined by a round robin algorithm on the unlocked entries Coherency of the TLB is maintained by software write transac tions to the SG_TBIA scatter gather translation buffer invalidate all register The tag portion contains a DAC flag to indicate that the PCI tag address 31 15 corresponds to a 64 bit DAC address Only one bit is required instead of the high order PCI...

Page 108: ...try is valid then a TLB hit has occurred and this page address is concatenated with ad 12 2 to form the physical memory address If the data entry is invalid or if the TAG compare failed then a TLB miss occurs A 15 2 Scatter Gather TLB Miss Process The process for a scatter gather TLB miss is as follows 1 The relevant bits of the PCI address as determined by the window mask regis ter are concatenat...

Page 109: ...V Physical Memory Address DAC Tag Addr 31 13 32 13 12 02 Base Offset TAG Data Scatter Gather TLB Scatter Gather Map in Memory ad_h 31 13 sent to TLB for PCI window hit DAC indicator also sent LJ 04277 AI4 63 40 39 32 31 02 0000000000000000000 n 1 20 19 31 n 1 20 00000000 Compare Logic W_DAC Wn_BASE Wn_MASK 0 33 n 11 10 Tn_BASE 000000000 XXXXX Window Hit Tn_BASE Select n 10 11111 n n 12 13 n 10 ...

Page 110: ...en for the 8MB to 16MB EISA region because this window incorporates the mem_cs_l logic PCI window 3 was not used as it incorporates the DAC cycle logic PCI window 1 was chosen arbitrarily for the 1GB direct mapped region and PCI window 2 is not assigned Figure 1 22 Default PCI Window Allocation 21164 Memory Space PCI Memory Space 4GB 4GB 2GB 1GB 1GB Scatter Gather Window 0 Direct Mapped Window 1 1...

Page 111: ...be made using the following two chips Intel 82374EB EISA System Component ESC Intel 82375EB PCI EISA Bridge PCEB The PCI EISA bridge provides address decode logic with considerable attributes such as read only write only VGA frame buffer memory holes and BIOS shadow ing to help manage the EISA memory map and peripheral component compatibility holes This is known as main memory decoding in the PCI ...

Page 112: ...of hole and MCSBOH bottom of hole registers define a mem ory hole region where mem_cs_l is not selected The granularity of the hole is 64KB The MARl 2 3 registers enable various BIOS regions The MCSCON control register enables the mem_cs_l decode logic and in addition selects a number of regions 0KB to 512KB The VGA memory hole region never asserts mem_cs_l Figure 1 23 mem_cs_l Decode Area 4GB 512...

Page 113: ...s_l Logic Consequently the window address area must be large enough to encompass the mem_cs_l region programmed into the PCI EISA bridge The remaining window attributes are still applicable and or required The Wx_BASE_SG bit in the W0_BASE register determines if scatter gather or direct mapping is applicable The W0_ MASK register size information must match the mem_cs_l size for the scatter gather...

Page 114: ... North First St San Jose CA 95134 USA Phone 1 408 544 4322 VisionTek 1175 Lakeside Dr Gurnee IL 60031 Table B 1 Samsung DIMM Part Number List Size Part Number of Bank Width ECC 16MB KMM374S203BTN 2 Bank KMM374S203BTL 2 Bank 72bit Yes 32MB KMM374S403ATN 2 Bank KMM374S403BTN 2 Bank KMM374S403BTL 2 Bank 72bit Yes 64MB KMM374S803AT 2 Bank KMM374S823AT 4 Bank KMM374S823ATL 4 Bank 72bit Yes 128MB KMM374...

Page 115: ...2 VisionTek DIMM Part Number List Size Part Number Width ECC 16MB VT16455 0 72bit Yes 64MB VT164 0 72bit Yes 128MB VT164V6 0 72bit Yes Table B 3 Viking Components DIMM Part Number List Size Part Number Width ECC 16MB VE2721U4SN3 DC01 72bit Yes 32MB VE4721U4SN3 DC01 72bit Yes 64MB VE8721U4SN3 DC01 72bit Yes 128MB VE16722U4SN3 DC01 72bit Yes Table B 4 QesTec DIMM Part Number List Size Part Number Wi...

Page 116: ...ble from United Machine and Tool Design River Road Fremont NH 03044 Phone 603 642 5040 Fax 603 642 5819 PN 70 32810 02 B 3 Power Supply An ATX form factor power supply suitable for use with the AlphaPC 164UX 3 3 V 5 V 5 V 12 V 12 V is available from Emacs Electronics USA Inc 1410 Gail Borden Place C 4 El Paso TX 79935 Phone 915 599 2688 PN AP2 5300F 300 W Table B 5 Dense Pac Microsystems DIMM Part...

Page 117: ...y is available from Axxion 11 B Leigh Fisher El Paso Tx 79906 Phone 915 772 0360 Fax 915 778 3200 PN DL17 Addtronics Industrial 43263 Osgood Road Fremont Ca 94539 Phone 510 490 9898 Fax 510 490 7132 PN EX 6890A California PC Products 205 Apollo Way Hollister Ca 95023 Phone 408 637 2250 Fax 510 490 7132 PN 6D3APD 6C6APD ...

Page 118: ...http www samsungsemi com You can also call or e mail to Samsung CPU Marketing Team Please use the follow ing information lines for support Samsung Alpha Products For documentation and general information Korea 82 331 209 3285 United States and Canada 1 408 544 4510 Europe 49 6196 663410 Electronic mail address alphainfo sec samsung com For technical support Phone 82 331 209 3282 Fax 82 331 209 449...

Page 119: ...500 MHz KP21164 500CN Samsung Electroncis 21164 Alpha microprocessor 533 MHz KP21164 533CN Samsung Electronics 21164 Alpha microprocessor 566 MHz KP21164 566CN Samsung Electroncis 21164 Alpha microprocessor 600 MHz KP21164 600CN Samsung Electronics 21164 Alpha microprocessor 633 MHz KP21164 633CN Samsung Electroncis 21164 Alpha microprocessor 667 MHz KP21164 667CN Motherboard Kits Order Number Sam...

Page 120: ... BX UM1 Title Vendor Alpha AXP Architecture Reference Manual PN EY T132E DP Call your local distributor or call Butterworth Heinemann Digital Press at 1 800 366 2665 Alpha Architecture Handbook1 PN EC QD2KB TE See previous entry Samsung 21164 Alpha Microprocessor Hardware Reference Manual KP164 HR1 0397 Samsung Electronics Ltd San 24 Nongseo ri Kiheung eup Yongin city Kyungki do Korea 449 900 Onli...

Page 121: ...CI BIOS Specification Revision 2 1 PCI Special Interest Group U S 1 800 433 5177 International 1 503 797 4207 Fax 1 503 234 6762 82420 82430 PCIset ISA and EISA Bridges includes 82371SB Intel Corporation Literature Sales P O Box 7641 Mt Prospect IL 60056 Phone 1 800 628 8686 FaxBACK Service 1 800 628 2283 BBS 1 916 356 3600 Super I O Combination Controller FDC37C666 Data Sheet Standard Microsystem...

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