Pioneer PX-7 User Manual Download

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Summary of Contents for PX-7

Page 1: ...ARTS LOCATIONS 23 5 EXPLODED VIEWS AND PARTS LIST 25 6 PACKING 28 7 CONNECTION DIAGRAM 29 8 SCHEMATIC AND P C BOARDS CONNECTION DIAGRAM 31 9 ELECTRICAL PARTS LIST 44 10 ADJUSTMENTS 48 11 INSPECTION ROM INSTRUCTION MANUAL 53 12 BLOCK DIAGRAM 69 13 CIRCUIT DESCRIPTION 73 PIONEER ELECTRONIC CORPORATION 4 i Meguro i Chome Meguro ku Tokyo 153 Japs PIONEER ELECTRONICS USA INC P O Box 1760 Long Beach Cal...

Page 2: ...ys Cable 1 5 m with 13 pin DIN plug Sound Source 3 voice 8 octaves 1 noise 8 envelopes C T I voice key click sound sound External stereo audio input signals 150 mV 50 kfi Output Internal speakers stereo Headphones stereo Line output stereo 150 mV 1 kfi Mixing control Computer sound mixing level control 15 dB Master volume control Externa sound muting control Interface System control Laser Vision P...

Page 3: ...1 2 BLOCK DIAGRAM ...

Page 4: ... area is not used Its size is determined by subtracting the stack area variable area and program area from the user area It can be sought by the FRE function Stack area in which BASIC returns and addresses are saved when FOR NEXT r GOSUB statements are executed f Area in which character strings includ ed in the character variables and array variables are stored The size of this area is the size de...

Page 5: ...ress latch AY 3 8910 HA1 W Data write or HA2 R Data read equivalent HA8 W Port A data write 8255A or R Port A data read equivalent HA9 W Port B data write R Port B data read HAA W Port C data write R Port C data read HAB W Mode set H90 W Strobe output bO latch output R Status input bl 1 is BUSY H91 W Print data latch output I O addresses from 80 to FF area prescribed as above for system use Empty ...

Page 6: ... put CS1H 4000 to 7FFF 4 CS2L Slot designation number of ad dresses 5 CS2H 8000 to BFFF 6 CS3L Slot designation number of ad dresses 7 CS3H C000 to FFFF B 0 S 7 Inf ut Keyboard return signal C 0 KBO 2 KB2 Keyboard scan signals 3 Output KB3 4 CASON Cassette control L ON 5 CASW Cassette write signal 6 CAPS CAPS lamp signal lights when low 7 SOUND Sound output based on software ...

Page 7: ... Input CONTROLLER 2 4 pin 2 RIGHT2 4 CONTROLLER 1 6 pin 1 TRGA1 CONTROLLER 2 6 pin 2 TRGA2 5 CONTROLLER 1 7 pin 1 TRGB1 6 CONTROLLER 2 7 pin 2 TRGB2 7 CASR cassette tape read B 0 CONTROLLER 1 6 pin 3 1 2 CONTROLLER 2 6 pin 3 High level 3 Out ut CONTROLLER 2 7 pin 3 4 CONTROLLER 1 8 5 CONTROLLER 2 8 6 Port A input select 1 Effective when port B bit 6 is low For CONTROLLER 1 2 Effective when port B ...

Page 8: ... 7 R EXTV Status indicating availability of exter nal video signal Low when available high when not available W Mute Line input signal muting 6 1 0 R INTEXV Interrupt available with interrupt flag 1 when external video signal is OFF Set to 0 when read W OVERLAY Hardware selection signal of superim pose non superimpose mode 0 for superimpose 1 for non superimpose 1 5 CONNECTOR 1 System control outp...

Page 9: ...GB connector Horseshoe shaped 8 pin DIN connector Pin No Signal Logical porality 1 2 GND 3 4 Horizontal sync signal Negative 5 Vertical sync signal Negative 6 RED Positive 7 GREEN Positive 8 BLUE Positive Round 8 pin DIN connector 6 Cassette interface connector INPUT or OUTPUT based on unit ...

Page 10: ... I O 5 D7 I 6 D3 I 7 D4 I O 8 DO I O 9 5 V 10 STB 0 11 GND 12 CAPS 0 13 GND 8 Printer connector Pin No Signal I O 1 PSTB 0 2 PDBO o 3 PDB1 0 4 PDB2 o 5 PDB3 o 6 PDB4 0 7 PDB5 o 8 PDB6 o 9 PDB7 o 10 NC 11 BUSY I 12 NC 13 NC 14 GND Round 13 pin connector Amphenol 14 pin connector ...

Page 11: ... WAIT I 8 INT 1 9 Ml o 10 BUSDIR I 11 IORQ 0 12 MERQ o 13 WR o 14 RD o 15 RESET o 16 Spare 17 A9 0 18 A15 0 19 All o 20 A10 o 21 A7 o 22 A6 0 23 A12 o 24 A8 0 25 A14 o 26 A13 o 27 A1 o 28 A0 o 29 A3 o 30 A2 o 31 A5 o 32 A4 0 33 D1 I O 34 DO I O 35 D3 I O 36 D2 I O 37 D5 I O 38 D4 I O 39 D7 I O 40 D6 I O 41 GND 42 CLOCK o 43 GND 44 SW1 45 5 V 46 SW2 47 5 V 48 12 V 49 SUNDIN I 50 12 V Input or outpu...

Page 12: ...t terminals The picture on the connected display is selected by operating the screen selector key on the keyboard m THROUGH The signals which were input to the rear panel input ter minals are output without being passed through the PX 7 s circuitry to the rear panel output terminals The sound supplied from the PX 7 is heard through the built in speakers KEYBOARD connector The keyboard cable is con...

Page 13: ... the video disc player to these terminals 2 AUDIO OUTPUT terminals R L Use these terminals to connect an external stereo amplifier They are used when the sound of the personal computer is to be passed through the stereo circuitry VIDEO INPUT terminal Connect the external video signal such as the video output of the video disc player to this terminal VIDEO OUTPUT terminal This is connected to the v...

Page 14: ... pack The control signals from the PX 7 are output here Use it when the unit is employed in combination with PIONEER S LD 1100 Laser vision player The control signals from the PX 7 are output here Use it when the unit is employed in combination with PIONEER S LD 700 Laser vision player Note See pages 18 through 21 when using the unit in combination with PIONEER S SD 26 component display or with th...

Page 15: ...ternal video source which has been connected to the PX 7 s video input terminal appears on the display COMPUTER The computer picture generated by the PX 7 appears on the display D Upper case indicator This lights when the CAPS LOCK key is pressed to enter upper case letters 3 Screen editing keys CLS HOME INS DEL These keys are used to edit the letters displayed on the screen Cursor keys These are ...

Page 16: ... of the keyboard either key may be used This is used to type upper case of the character which has lower case and uppercase It is locked when pressed once and the lamp to the left of the key top lights It is released when pressed again When character keys are pressed with this key locked upper case are typed and when the key is released lowercase are typed This is used to type graphic characters W...

Page 17: ...ric keys alone are pressed S BBBHBBBBBBBEBBg BBS ED EDBBBBQBBQElBmBBD e edbbbbbbbbbbbbmJ m EBBBBBBBBBBBEEB StB ed pibi i h nn b When the alphanumeric keys are pressed while the 1 SHIFT 1 key is depressed E EE m SBBBBBBBBBBBBBg BBB ED BBBBBBBBBBBQBnn e ebbbbbbbbbbbbbmj ed ED EBBBBBBBBBBBEDO EDGE 110 m c When the alphanumeric keys are pressed while the GRAPH I key is depressed E S S BBBBBBBBBBBBBBg ...

Page 18: ...is depress ed E mi BQHBQQEBEEEBQElg BBS B SHHQQHHQQQmQGTD b qhbqqqqbqqqqeMJ m SQQEB0Q00Q000 00 B Hf IB m f When the alphanumeric keys are pressed while the I CODE I and I SHIFT 1 keys are depressed i 1 1 rr SDBBBDBBBDBBDDg BBS ED HBBBBDBHBBBBBnD b ebbbbbbbbbbbbbmJ m SBBQQQ0O0DQ0B EDCD E3 8R I H ED I Note SCREEN MODE 0 is for text only Part of the graphic characterfont may disap pear Use SCREENMODE...

Page 19: ...r m 1 SHIFT 1 1 P 1 I caps i m 1 CAPS 1 1 SHIFT I T T GRAPH 1 I P I I GRAPH 1 SHIFT 1 IT 1 CODE 1 1 P 1 1 CODE 1 1 SHIFT I m P Lower case P Upper case P Upper case P Upper case B Graphic symbol mode Graphic symbol mode u Special character mode n Special character mode Key pressed Typed character m i SHIFT 1 m i caps i m I CAPS 1 1 SHIFT m 1 1 f 1 GRAPH 1 1 i 1 1 CODE 1 m 1 CODE 1 1 SHIFT 1 m Key p...

Page 20: ...ripheral units but also makes the most of its features through coupling with a video disc player If a VCR and an audio system are further added systems completely unavailable in the past can be built up The system configuration of the PX 7 is shown in the figure below SD 26 Component display unit 20 ...

Page 21: ...3 DISASSEMBLY ai ...

Page 22: ... Remove the 2 screws Remove the 1 revet J ...

Page 23: ...ts Stock Control the fast moving items are indicated with the marks and GENERALLYMOVES FASTER THAN This classification shall be adjusted by each distributor because it depends on model number temperature humidity etc Rear Panel View Astrain relief AEC 327 DIN socket 8P OUTPUT 3 AKP 086 DIN socket 8P DATA RECORDER AKP 085 Top View I A Power transformer T1 ATS 250 Plunger switch ASR 085 Main assembl...

Page 24: ...Top View II Relay ASR 084 CPU main assembly GWP 141 Main assembly GWM 419 HB GWM 434 HE KEY BOARD ASSEMBLY Bottom View ...

Page 25: ...PX 7 5 EXPLODED VIEWS AND PARTS LIST A B C D 1 2 3 ...

Page 26: ...4 5 6 4 ...

Page 27: ...sembly 11 AAY 294 12 AAY 295 13 AAY 296 14 ANE 591 15 ANY 101 Push knob F VIDEO AUDIO 106 Reset knob RESET 107 Power knob POWER 108 Bonnet 109 Front panel assembly 1 1 0 Slot connector assembly Joy stic connector assembly Key board connector assembly SP holder Front chassis 16 AAH 111 17 ANL 034 18 ABH 158 A 19 AEC 327 20 A EC 441 Cartridge door Door Shaft Door Spring Strain relief Plastic rivet 1...

Page 28: ...Marie No Part No Description Marie No Part No Description 1 ADE 094 2 ARB 697 3 ARB 698 4 A HA 405 5 AHA 406 Cord Instruction manual Basic manual Packing A Packing B 6 AHB 154 7 AHE 625 8 ARB 703 101 102 103 Packing case P Basic manual 28 ...

Page 29: ...J 1 I 2 7 CONNECTION DIAGRAM 1 1 I 2 I 3 ...

Page 30: ......

Page 31: ...PX 7 8 SCHEMATIC AND P C BOARDS CONNECTION DIAGRAIV ...

Page 32: ...I_ I 4 I 5 I 6 GWM 4I9CHB LED 6 r ...

Page 33: ...J ...

Page 34: ...4 5 6 4 5 6 ...

Page 35: ...7 8 9 I 7 8 9 ...

Page 36: ...4LS02N SN74LS30N SN74LS04N SN74LS32N SN74LS08N SN74LS05N SN74LS74AN SN74LS38N 16 Pin M74LS30P SN74LS367AN SN74LS157N SN74LS139N SN74LS1 53N AN5620X RAAARR lj M 20 Pin SN74LS374N 28 Pin M5L2764 YM 2301 23908 LH0080A YM 2149 M5L8255AP 5 PD8 001 42 Pin MB1 I S1 12 8 Pin M5218P SN75140P 18 Pin TMS4416 15NL M5M4416P 15 11 12 36 r 10 ...

Page 37: ... X 7 1 8 2 CPU MAIN ASSEMBLY 3 1 2 1 ...

Page 38: ...4 5 6 SLOT CONNECTOR ASSEMBLY 4 5 6 ...

Page 39: ...41 7 8 9 Jflp JOY STICK CONNECTOR ASSEMBLY I 7 8 9 ...

Page 40: ...10 11 I 12 I 10 I 11 I 12 ...

Page 41: ...1 1 2 3 ...

Page 42: ...6 I 4 5 6 ...

Page 43: ...7 PX 7 8 9 7 r ...

Page 44: ...WM 434 HE Phone amplifier assembly GWH 184 Switch assembly Filter assembly Volume assembly LED assembly CPU main assembly GWP 141 Switch assembly Slot connector assembly Joy stick connector assembly Key board connector assembly Key board assembly A T1 A S2 A FU101 A C80 Power transformer 240V ATS 250 Push switch POWER ASG 539 Fuse AEK 036 AEK 502 Capacitor ACG 504 0 047 AC400V AC power cord Speake...

Page 45: ...5 C203 Cl 46 C201 CEAS100M50 C285 C311 CEAS101M10 CEAS102M25 CEAS221M10 CEAS3R3M50 CEAS330M25 CEAS331M10 CEAS4R7M50 CEAS470M10 CEAS470M25 CEAS471M10 CKCYB102K50 CKCYB222K50 Cl 08 CKCYB331K50 C205 CKCYB332K50 C111 Cl 19 C122 C123 CKCYF103Z60 C125 C127 C136 C147 C287 C110 C124 C137 CKCYF473Z60 C129 C130 C148 Cl 17 Cl 18 C319 C320 Cl 45 C150 C140 Cl 41 C151 C321 C322 C345 Cl 49 C152 CQMA103J50 CQMA12...

Page 46: ... Mark Symbol Description Part No IC43 IC44 All resistors RD1 8PM J IC6 ICS 1C 10 IC45 OTHERS Mark Symbol Description Part No IC32 Terminal HEADPHONE AKN 056 IC35 IC20 IC21 Volume Assembly RESISTORS Mark Symbol Description Part No IC2 IC5 VR107 Slide volume 100k ACX 142 IC12 VR108 Slide volume 50k ACX 143 Q1 Q2 Q4 Q9 LED Assembly 05 Q8 Q10 Q11 SEMICONDUCTOR D18 Mark Symbol Description Part No D1 D5...

Page 47: ...ERS Mark Symbol Description Part No C34 CQMA682J50 DIN socket 13P AKP 074 C68 C70 C36 C59 C69 CEAS331M6 CEAS221M10 CCCH101J50 CCDSL121J50 Key Board Assembly SEMICONDUCTORS Mark Symbol Description Part No RESISTORS Mark Symbol Description Part No C C C C MPD4071BC TC40H367P SN74LS145N SN74LS174N R17 R64 R76 RA8S OOOJ LD1 AEL 421 Other resistors RD1 8PM OODJ D1 D3 2 1K261 OTHERS SWITCHES Mark Symbol...

Page 48: ... R B Adjustment 3 Horizontal Position Adjustment 4 Color Subcarrier Frequency Adjustment 5 Color Subcarrier Suppression Adjustment 6 Black Level Adjustment 7 Switching Spike Elimination Adjustment 8 Hue Adjustment 9 Confirmation by Check ROM AB ...

Page 49: ...e and record the TP 3 voltage A when noise becomes apparent in the bars 10 Next turn VR103 slowly clockwise and again record the TP 3 voltage B when noise becomes apparent in the bars 11 Finally adjust VR103 to obtain the TP 3 voltage which is half way between voltages A and B P BASIC Versionjl lj Copyright 1985 by PIONEER BASIC MODE SELECT 1 MSX BASIC P BASIC 2 MSX8ASIC PUSH 1 or 21 White charact...

Page 50: ...ress the SUPERIMPOSE key to obtain a composite display Compare the color bars in this composite screen with the color bars in the previous computer mode screen and adjust VR102 during the composite screen display to keep the color bar displacement in the horizon tal direction within the width of the narrow color bar see Fig 10 8 Monitor TV screen same as in R B adjustment 10 4 COLOR SUBCARRIER FRE...

Page 51: ...onnect an oscilloscope to the VIDEO OUT terminals with the PX 7 in computer mode Observe the video synchronizing signal 2 Adjust VR106 to minimize the carrier which is superimposed on the video synchronizing signal see Photo 10 2 Photo 1 0 2 10 6 BLACK LEVEL ADJUSTMENT 1 Press the SUPERIMPOSE key to switch to com posite mode 2 Check that the external video signal output level lies within the lVp p...

Page 52: ...ode 2 Enter the COLOR 4 4 4 input and press the return key to obtain an all blue screen 3 Adjust VR101 0 0 2 so that the blue hue output obtained from the computer is sym metrical about the U axis as indicated in Fig 10 13 and make sure that the external signal burst is fully coincident with the vectorscope burst point Adjusting without a vectorscope rough adjustment 1 Press the SUPERIMPOSE key to...

Page 53: ...electing a mode by keyboard input key in a suitable character to check for normal key input If key inputs are normal switch the power off and insert the INSPECTION 1 car tridge into the cartridge slot in the front of the unit to commence the test 2 If BASIC fails to start open the bonnet and remove IC13 P BASIC ROM from its IC socket Repeat the start procedure to see if BASIC will start up or not ...

Page 54: ...to that test on the menu screen 3 When a test 1 thru 6 is executed the pro gram returns to the menu screen upon comple tion of the test or when the SPACEl key is pressed 4 The aging test 0 consists of a loop test execut ed in the following sequence To quit this loop and executed another test either press the RESET button to return to the BASIC MODE SELECT menu or press the I CTRLI and ISTOPI keys ...

Page 55: ... in all addresses 4000H thru 5FFFH in the P BASIC ROM IC13 is checked to see that it comes to FFH VRAM TEST OOH 55H AAH and FFH data is written within the 3800H thru 3A98H VRAM address range and is then compared with the read data Since the screen settings would be destroyed it is not possible to check all addresses by this test Again the INSPECTION 2 cartridge must be used if a check is desired V...

Page 56: ...CDEFG HIJKLMNOPQRSTUVWXYZ abcdefghij klmnopqrstuvwxyz 3 Controller Test Testing of CONTROLLER 1 and CONTROLLER 2 port Connect PX JY8 to the selected CONTROLLER port 1 The graphic characters shown in the accompa nying diagram are shifted and leave a trail depending on the direction of the grip but cannot be moved beyond the edge of the screen FORWARD Fig 11 6 Controller test 2 A beep sound is gener...

Page 57: ...creen to enable key inputs under MSX BASIC control If an abnormal condition exists however resulting in runaway status or suspended operation it will not be possible to detect that condition while under MSX BASIC control In this case if the inspection 2 ROM made ready when the power was switched on or the RESET switch pushed can be activated and various checks executed the location of the abnormal...

Page 58: ...ime the STEP button is pressed CONTINUE Tests executed continuously in succession useful in aging test After first removing the bridge connecting JPA to JPB repaired from the component side or the bridge connecting JPC to JPD repaired from the soldering side connect TP1 to TP3 and TP2 to TP4 to interchange slot 0 and 1 Insert the INSPECTION 2 cartridge in the front panel CARTRIDGE slot Adjust the ...

Page 59: ... area used as program work area is checked by tests and 6 Table 11 1 5 8000 80FFH TEST COOO COFFH TEST WORK AREA ADDRESS OK OK 8000 80FFH OK NG 8000 80FFH NG OK COOO COFFH NG NG CANT CONTINUE Fig 11 11 Sound output and LED lamps STEP 2 Title Display When the STEP button is pressed again after completing STEP 1 the title is displayed on the screen see accompanying diagram and the PSG tone is stoppe...

Page 60: ...PX 7 sn Fig 11 14 PPi test flow chart ...

Page 61: ... as long as one of the above pairs is operating If both pairs are NG however subsequent tests cannot be executed The CAN T CONTINUE message appears on the screen an accompanying tone is generated and the program is halted Rather than a defect in the RAM itself NG condi tions are usually due to a failure in the access stage Therefore when checking the circuitry check that RAS CAS WE OE ADDRESS LINE...

Page 62: ...g of 7EH data 8100 BFFF 00 NG 8100 7E 55 NG 8100 7E AA NG 8100 7E FF NG 8100 7E If a NG condition occurs during this test the pro gram proceeds to the next routine without check ing the remaining addresses in NG routine Hence there is only a single NG address data output for any one routine That is in the above NG display example it is not possible to tell whether the remaining addresses from 8101...

Page 63: ...ds immediately to the ROM TEST To ROM TEST F ig 1 1 1 7 V RAM test flow chart STEP 6 Rom Test The ROM TEST is divided into the P BASIC ROM TEST and the MSX BASIC ROM TEST 1 Check to see that P BASIC ROM address 4000 4001 4010 thru 4012H data is as shown in the following table Table P BASIC ROM address data 2 All P BASIC ROM address data from 4000H to 5FFFH is summed addition of all bytes with no c...

Page 64: ... of the MSX BASIC ROM is stored in addresses 1500H thru 157FH of the INSPECTION ROM IIMIJlii INSPECTION 2 ROM The MSX BASIC ROM test is executed by checking the above data and the check sum of all MSX BASIC ROM bytes Note that since this test is based on the MSX UK version 84 6 29 FIX a NG test result may be obtained for other normal ROMs if the contents of the ROM differ due to subsequent version...

Page 65: ...PX 7 END is displayed on the screen when the ROM test is completed and the program returns to the same output tone and LED pattern as in the beginning Fig 11 20 Fig 11 20 MSX BASIC ROM test B5 ...

Page 66: ... 9 0 0 0 0 0 0 9 PPI TEST 1 When result isOK 0 00 O O O 1 OK When result is NG O O O O 1 NG BEEP Comment Meaning of LED patterns OOOO OOOO L r1 l_i i i i i Test progress Test no rh Test result 1 rH 1 Now testing O 1 O O O 9 Test No 1 Output of result O 1 O O O Test No 2 OK O O f NG O O Test No 10 O Test No 1 1 Binary display All steps described below are executed in this sequence Beep tone gener a...

Page 67: ...8100 7E AA NG 8100 7E BEEP BEEP FF NG 8100 7E BEEP 8 Write read and verify STEP PUSH addresses C100 thru Now testing o o o o o o C100H FFFFH 00 OK When result is OK 0 00 o o o 55 OK AA OK FF OK 00 NG C100 7E BEEP When result is NG o 0 O 0 55 NG C100 7E AA NG C100 7E BEEP BEEP FF NG C100 7E BEEP STEP5 V RAM TEST STEP PUSH 9 Write read and verify Now testing o o o o o Change in screen display V RAM ...

Page 68: ...udio system NG o No PSG IC5 A B and C outputs Check signal between PSG and CPU Check gate array PSG signal Check clock input o A B and C obtained but no sound Check ASCL and ASCR and check Q10 Qll if NG Check the analog ass y audio system 4 LEDs DISPLAY and SOUND all NG Have slots 0 and 1 been switched Is the CPU clock OK Is address bus AO thru A1 5 normal Is data bus DO thru D7 normal Check signa...

Page 69: ...12 BLOCK DIAGRAM 70 ...

Page 70: ...70 ...

Page 71: ......

Page 72: ...PX 7 71 72 ...

Page 73: ...th three built in 8 bit I O ports PAO thru PA7 PBO thru PB7 PCO thru PC7 Mode A used with PAO thru PA7 set as output PBO thru PB7 set to input and PCO thru PC7 set to output PAO thru PA7 allocated to slot selection PBO thru PB7 PCO thru PC3 and PC6 to keyboard I F PB4 and PB5 to data recorder I F and PC7 to sound output 7 Keyboard Interface Output of scan signals to keyboard key matrix and input o...

Page 74: ...nal The color subcarrier 4 433618 MHz is used as the carrier two signals 90 out of phase with each other for the carrier color signal modulator In computer picture mode PLL operation is stopped and the color subcarrier frequency becomes the free running frequency This carrier is also used as the reference clock for the synchronizing pulse generator 8 Horizontal Synchronizing Signal Processing Circ...

Page 75: ...e VDP R Y and B Y signals to the color subcarrier 4 433618MHz The color subcarrier suppression adjustment control VR106 is made up of the bias adjustment volume of the carrier color signal modulator And the voltage regulator supplies power for the carrier color signal modulator bias circuit 3 Mixing circuit and carrier color signal filter The R Y and B Y carrier color signals generated in the colo...

Page 76: ...nals to speaker and headphone driver levels C Through Switch Circuits 1 Through Relay Switching relay for output of external video and audio signals applied to the VIDEO and AUDIO INPUT terminals direct to the VIDEO and AUDIO OUTPUT terminals through or input to the ass y processing circuits normal The relay consists of two plungers PM1 and PM2 and relay switches RY102 l 8 thru 8 8 in an integrate...

Page 77: ... Level Diagram 77 ...

Page 78: ...OUTPUT VIDEO OUTPUT VIDEO INPUT ra RF OUTPUT KEYBOARD 30 AUDIO CASSETTE Data recorder CONTROLLER 1 CONTROLLER 2 g STEREO AUDIO INPUT o STEREO AUDIO OUTPUT L TOW BUILT IN R SPEAKERS HEADPHONES O SYSTEM CONTROL OUTPUT 1 O SYSTEM CONTROL OUTPUT 2 Z 0 SYSTEM CONTROL OUTPUT 3 O SYSTEM CONTROL INPUT DENOTES ANALOG BOARD l F INTERFACE Fig 13 1 Block diagram 7B ...

Page 79: ...is of MSX standards It is also possible to obtain a WAIT by WAIT request EXT WAIT from an external source applying the input via the slot section if necessary from the external device Fig 13 4 Wait circuit 1 IC35 1 2 latches Ml L at the leading edge of the T2 state p in the Ml cycle The IC35 l 2 Q output is thus switched to L 2 The CPU reads the L level applied to the WAIT pin from the IC35 l 2 Q ...

Page 80: ...ress bus is connected directly to the ROM RAM circuits but via buffers 74LS367 IC6 thru IC8 to other circuits ADDRESS 13 2 7 Data Bus The data bus is connected to the various LSIs ICs and cartridge connectors via a bidirectional buffer 74LS245 IC9 Bidirectional buffers control the data direction depending on whether data is applied to or receiv ed from the CPU this control being executed via the D...

Page 81: ...0000 H thru 7FFF H of slot 0 32K bytes and is normal ly selected when the power i s switched on This MSX ROM is selected when MERQ L RD L and SLTSL0 L at memory addresses 0000 H thru 7FFF H A15 L And as will be described later 13 7 1 an L output from SLTSL0 is generated automatically when the power is switched on or when the RESET button is pressed resulting in the MSX ROM being selected and MSX B...

Page 82: ...ress strobe control signals plus various MPX signals for the multiplexer These signals are generated in the gate array 2 The MPX signal is used in row column address switching prior to passing addresses to the RAM 3 Although the RAS signal is passed via a logic circuit for reasons related to the gate array it may be considered as equivalent to the MERQ signal 4 Apart from the refresh cycle the MPX...

Page 83: ... A13 are re quired to specify 16K bytes 2 14 addresses D RAMs however are only equipped with address input pins for up to 8 bits AO thru A7 Hence AO thru A13 is divided into row address AO thru A7 and column address A8 thru A13 with ad dressing operations being executed in two steps 1 Addresses are divided into row and column addresses by multiplexer controlled by the MPX signal 2 In the DORAM the...

Page 84: ... decoded by a 3 to 8 LINE decoder and I O access signals generated at 8 byte intervals from 80H to BFH are allocated to each I O As a result I O addresses 90H thru 97H are allocated to the printer I F 98H thru 9FH to the VDP AOH thru A7H to the PSG and A8H thru AFH to the PPI The I O map is outlined in the table below TW1 Fig 13 14 I O Address decode circuit Table 13 3 I O address allocation HA0 H...

Page 85: ...slot 2 by the memory mapped I O method for exchange with the CPU The extended I O interface is used in video audio and system control with accessing executed by AO thru A15 SLTSL2 WR and RD to generate the following signals LCONW L when 7FFEH writing LCONR L when 7FFEH reading VCONW L when 7FFFH writing VCONR L when 7FFFH reading The bit allocation for memory addresses 7FFEH and 7FFFH is outlined ...

Page 86: ...ternal video signal stops in superimpose or external video mode INTEXV serves as the CPU interrup signal and INTEXV serves as the corresponding status signal 2 Since point A is at H and point B at L when RESET is applied point C and point D are switched to H resulting in INTEXV also being switched to H And when the VCON register is read INTEXV 0 is obtained from bit 0 3 When EXTV is changed from L...

Page 87: ...l muting control LMUTE has to be changed from L to H An integrating circuit R319 C305 is used to prevent response in the left channel muting circuit Q303 Q305 during this L H change And to ensure equal response times in both left and right channels an integrating circuit R320 C306 is also included in the right channel muting circuit Q304 Q306 Left channel MUTING ON OFF W m V m 77777777 Right chann...

Page 88: ...REMO which serves as the source signal for wired remote control 3 CREMO is generated by on off switching of the output obtained by dividing REMCLK by 12 based on UREMO 4 CREMO is an infra red LED drive signal connected by coupler cord for infra red remote control operation Q9 is a driver transistor which is no longer necessary with LD 1100 since direct connection to the control terminal is possibl...

Page 89: ...no SELECTI input SELECTO is changed to L to enable LREMO when SEL CONT is 5V but is changed to H to disable LREMO when SELCONT is 0V 5 The SELECTI input is applied to the stereo mini jack R terminal the L terminal being for EXTREMI inputs EXTfiEMI 6 If the SD 26 control output is connected by mini plug to the stereo mini jack as shown in Fig 13 25 SELECTI makes contact with the plug GND and is con...

Page 90: ...h is pressed During normal operatio When external synchronizing signal SYNC is applied during superimpose or external video 1 With RESET SYNC leading edges serving as horizontal synchronizing pulses the VDP internal counter is reset in a horizontal synch ronous state 2 And with synchronizing pulses greater than 7 2 nsec serving as vertical synchronizing pulses the internal vertical counter is set ...

Page 91: ...PC port Four lower bits PCO thru PC3 Key scanning signal generation Four higher bits PC6 CAPS lamp switching PC4 Cassette I F remote relay control PC5 Cassette data writing PC7 Key click tone source Each PPI port is selected on the basis of the status of AO Al WR and RD when PP1 L and CS L see Table 13 8 The formation of address images is prevented by using A2 in CS Note that the MSX is used in mo...

Page 92: ...s l_ and 1 denotes H level Slot selection Slots are selected by PA ports in the following way The function of the CSnH and CSnL signals where n 0 to 3 for PAO thru PA7 is to specify addresses for each 16K bytes and to specify the corresponding slots 0 thru 3 for those addresses These CSnH L signals can be considered as CSn and SLT H L elements in the following way 1 CSn where n 0 to 3 specified ad...

Page 93: ...et to 1 That is PAO CSOL 0 If 11100100 E4 H is set in PAO thru PA1 CSOH 0 PA7 the CPU can handle the memory PA2 CS1L 1 area shown in the diagram below PA3 PA4 CS1H CS2L PA5 CS2H PA6 CS3L PA7 CS3H 1 consecutive 64K byte memory This method also prevents the danger of bus collisions if identical address memories in different slots are accessed simultaneously Fig 13 31 Slot selection ...

Page 94: ... to IC33 l 2 Output circuit The PPI pin 12 CASW PC5 output is passed via a bandpassfilter consisting of C30 C31 and R22 thru R24 resulting in an output quasi audio signal being passed to CMT OUT AUDIO CASSETTE INTERFACE C36 13 7 3 Keyboard l F The number of leads in the connecting cable to the separated keyboard is reduced by using a partially bidirectional bus line The bidirectional section of th...

Page 95: ...H I O READ INSTRUCTION FETCH I O WRITE m M hM 7777m OpBEJiDOiTV i i lfti DATA 1 j I y__un BIDIRECTIONAL BUS s y i _jff YA THRU YD LATCH BIDIRECTIONAL BUS W 777 777777771 TM wm7m mnrmmr OUT VIOUS DATA S C pE j_AY 2 1 kxo 3 in 1 I DATA READ i r Fig 13 34 Keyboard interface timing chart ...

Page 96: ...B used in a control ler I F for joystick and tablet connections The PSG is accessed by BDIR and BC1 with BC2 and A8 at H level and A9 at L level A2 is applied to the A9 input to prevent generation of address images BDIR and BC1 are both changed to H by writing the I O address AO H and the register address is then latched by the PSG Data writing is executed when BDIR is changed to H with BC1 remain...

Page 97: ...put is not used in this case and is left at H level 2 IOB are used as output only The IOBO thru IOB3 pins are connected by open collector via respective buffers 74LS04 IC39 and 74LS05 IC41 IOBO and IOB1 being connected to pins 6 and 7 of controller 1 and IOB2 and IOB3 being connected to pins 6 and 7 of controller 2 IOB6 is used as a selector signal in controller 1 and 2 switching L controller X H ...

Page 98: ...s the resistances R79 thru R82 for constant power ratio In the same way the PPI IC4 PC port bit 7 output SOUND is mixed and localized centrally via C56 R77 and R78 and the sound input SUNDIN from the cartridge slot is mixed and localized via R15 R16 R96 C64 C63 R91 and R92 Thus the audio sound outputs ASCL and ASCR are formed and passed to the analog ass y via pins 4 and 2 of J100 The ASCL and ASC...

Page 99: ... and passed to PSTB at the leading edge of WR thereby obtaining PSTB via the IC38 and IC40 buffers IC40 is connected in parallel for fan out enlargement 3 90R BUSYEN is formed with 90H RD to enable the BUSY input three state buffer and input of the BUSY signal to Dl 4 91W LPTE is formed with 91H WR and DO thru D7 are latched at the leading edge of WR to obtain the PDBO thru PDB7 outputs With the Q...

Page 100: ...Fig 13 41 Audio system block diagram ...

Page 101: ... of the SHIFT key can be keyed in This shift mode is switched on or off in dicated by the lamp being switched on or off The above operations are handled by MSX BASIC software When the SHIFT key is used together with the GRAPH or CODE key as indi cated in the above table three keys must be pressed together Consider an example where the SHIFT GRAPH and 0 keys are pressed together Current la is passe...

Page 102: ... 3 18 j 3 19 pi p ocessoH I I J LOOP _J I r FILTER _ VC 1 3 22 THROUGH S fl 3 23 POWER SUPPLY Cl VIDEO SIGNAL mrnrTmma nrtTtTrnf TTTT HSrHc W H 64 S 15 625 kl 102 ...

Page 103: ...here is no signal And since the time constant determined by the Q105 emitter resistance R113 and capacitor C104 is sufficiently large enough Q105 is turned off when the Q104 emitter voltage exceeds the Q105 cut off voltage resulting in the Q105 collector output being changed to L level Horizontal synchronization 1 ps div a VIDEO input waveform 200mV div b Waveform 3 composits synchronizing signal ...

Page 104: ...ircuit see Photo 13 3 waveform a Then following a DC level shift at D137 to ensure that the Q107 gate potential does not exceed 5V IC102 gate array output voltage condition the IC102 burst gate pulse BGP2 see Photo 13 4 waveform is applied to the gate of Q107 thereby applying only the color burst signal from the chroma signal to the pin 8 input see Photo 13 3 waveform b This color burst signal app...

Page 105: ...lse intervals enlarging the pulse width will prevent the generation of color bursts in the carrier color signal modulator Therefore the width is limited to about 800ns and the pulse position is set near the front porch of the internal external horizontal synchronizing signal thereby eliminat ing the influence of the blanking see Photo 13 4 waveform b If the nth line vector of the color subcarrier ...

Page 106: ...Fig 13 49 Hue changes at VIDEO OUT Synthesis mode only IC101 PIN 4 2V div b IC101 PIN 8 1 V div Photo 13 3 Color burst sampling Photo 13 4 VIDEO IN PAL PULSE BGP2 and BGP1 timing 4 OB ...

Page 107: ...h line outputs Q108 and Q109 outputs Photo 13 6 Reproduced color subcarrier vector n 1 th line a waveform B Y axis synthesized color subcarrier output IC101 pin 11 b 7 waveform R Y axis synthesized color subcarrier output IC101 pin 10 Photo 13 7 Reproduced color subcarrier outputs 107 ...

Page 108: ...pins 6 and 8 see Photo 13 8 and Photo 13 9 G and OVLYF Generator Circuit see Fig 13 50 The G and OVLYF signals are obtained from the three Y R Y and B Y outputs from the VDP TMS9129 described above The G signal is obtained by addition to the other signals in accord ance with the following equation 4 G Y 0 51 R Y 0 19 B Y The 0 51 R Y 0 19 B Y addition is executed by R207 R208 and the inverted sign...

Page 109: ...d if a flag is present when the G signal is concerned Hence to prevent the generation of a G signal in the external signal section the G output is blocked while OVLYF is at H level that is while the external video signal is displayed as a result of OVLYF being inverted and added to the analog signal pin 3 of IC104 see Fig 13 51 The OVLYF signal exists in the following states Table 13 13 Mode OVLYF...

Page 110: ...hoto 13 9 a TP 1 DC shift B Y signal 500mV div b TP 3 VR103 comparator reference voltage 500mV div c IC104 PIN 7 OVLYF signal 5V div Photo 13 11 OVLYF in computer mode Picture synthesis flag interval a TP 1 DC shift B Y signal 500mV div b TP 3 VR103 comparator reference voltage 500mV div c 1C 1 04 PIN 7 OVLYF signal 5V div Photo 13 12 OVLYF in picture synthesis mode a RGB OUTPUT G OUTPUT 5V div Wh...

Page 111: ... vary due to variations in the VDP and buffers For this reason the bias voltage applied to IC107 can be varied by VR106 carrier suppression adjustment control to ensure that IC107 balanced modulator is properly balanced The outputs from pins 1 and 9 are mixed by R269 R270 for carrier color signal modulated by IC107 to obtain the X part of the PAL system composite video signal in equation 1 See Pho...

Page 112: ... type transistors In the bias circuit too temperature compensation involves the use of similar pnp and npn transistors Since regulated power voltage is required by the carrier color signal modulator circuit IC107 and the bias circuit the voltage is regulated a second time by the triple terminal regulator IC116 Carrier color signal filter mixing amplifier burst ATT The carrier color signal output f...

Page 113: ... Y IV div Photo 13 15 Computer mode EXTERNAL VIDEO PICTURE AREA Picture synthesis flag EXTERNAL VIDEO PICTURE AREA a WAVEFORM B Y IV div b WAVEFORM R Y IV div c ACHROMATIC LEVEL d PICTURE SYNTHESIS FLAG LEVEL Photo 13 14 Synthesis mode a WAVEFORM D B Y IV div b WAVEFORM R Y IV div c ACHROMATIC LEVEL Photo 13 16 Synthesis mode 113 ...

Page 114: ... a VIDEO OUT terminal output External white 100 puls internal 16 color bar 75 ohm load 200mV div b f H Y input waveform 500mV dlv Photo 13 18 With overlay flag eliminator a Carrier color signal IV div b R Y signal IV div B Y signal IV div Photo 13 19 Computer mode 16 color bar a CARRIER COLOR SIGNAL IV div b R Y SIGNAL IV div B Y SIGNAL IV div Photo 13 20 Synthesis mode 16 color bar 114 ...

Page 115: ...ircuit This circuit switches the external video signal and computer signal outputs in response to the OVLYF signal from pin 7 of IC104 When OVLYF is H pins 5 and 13 of analog switch IC108 are also changed to H to select the external video signal And when OVLYF is L pin 12 of IC108 is changed to H to select the computer signal the output signal being obtained from pin 11 of IC108 Video amplifier Th...

Page 116: ...enerated The error voltage from the gate array phase comparator comparison frequency of 3 90625kHz in synthesis mode and 3 903kHz in computer mode is passed to the Q111 Q112 loop filter The filter output is then applied to the D101 variable capacitance diode to control the VCO The VCO oscillates on the basis of the 4 433618MHz color subcarrier signal during computer mode and on the basis of the fr...

Page 117: ...of this output is divided once by 684 and again by 4 overall division by 2736 to become a 3 903kHz comparator signal to be applied to the phase comparator The phase comparator output thus forms a loop with the loop filter and VCO which in turn forms a PLL oscillator circuit based on the divided signal obtained from the color subcarrier A horizontal synchronizing signal obtained by dividing the VDP...

Page 118: ...8 isec resulting in output of BGP from pin 16 for use in burst ATT circuit switching The same burst gate generator is also used to generate BGP2 and BGP1 outputs for control of the pin 19 pin 21 open drain output burst sampling circuit Relevant waveforms are shown in Photo 13 24 APPROX 450nS 3 6 3 SJJS Fig 13 56 Relevant waveforms in computer mode Fig 13 57 Synchronizing pulse generator Computer m...

Page 119: ...odes the hori zontal synchronizing signal frequency pulse width approximately 3 5 rsec is obtained from pin 3 EXHP1 The signal synchronized with the pin 3 output and applied to pin 4 is generated by the horizontal synchronizing signal processing circuit This signal is applied to a frequency divider 1 4 in the gate array before being passed to the phase comparator as a 3 906kHz reference signal Whe...

Page 120: ...PX 7 G8a G8b G8c EXHP1 Horizontal synchronizing signal IL_ n n 1 n n i 3 5jts n n n n r 64 isec Fig 13 58 Relevant waveforms in synthesis mode 120 ...

Page 121: ...The THROUGH switch is used to switch video and audio left and right channel signals to the internal circuits NORMAL where superimposing sound mixing and other processing is executed before the signals are passed to the output or directly to the video and audio left and right channel outputs bypassing the internal circuits THRU Since there is a number of circuits to be switched together with the po...

Page 122: ...H thereby increasing the level of m in accord ance with the delay circuit When the m level reaches the IC113 threshold level n is changed to L Q401 is turned off p is changed to H and the PM is switched off thereby completing the plunger drive operation at t4 Since current is passed to PM2 from C406 during the t2 thru t4 interval the e level decreases but is increased again according to the R414 C...

Page 123: ...CHARGE STORAGE CIRCUIT POWER OFF ON qff SIOI NORM THRU NORM j Fig 13 63 Timing chart ...

Page 124: ... permitted While the HB model power cable has not been fitted with a plug HE model has been fitted with the European conti nental plug The line filter consisting of L105 C414 C415 C416 C418 C419 and C420 reduces power line noise for improved operational stability D127 is the power indicator LED red and D133 diode is inserted to prevent back current The 5V and 12V power lines are regulated by bridg...

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