HP 271308 User Manual Download

Page: 1 / 122

Summary of Contents for 271308

Page 1: ...T PACKARD COMPANY Roseville Networks Division 8000 Foothills Boulevard Roseville California 95678 Technical Reference Manual Flin HEWLETT PACKARD Card Assembly 5061 4929 Date Code A 2318 Manual Part No 27132 90007 E0385 Printed in U S A March 1985 ...

Page 2: ...nual will contain new information as well as updates First Edition March 1985 NOTICE The information contained in this document is subject to change without notice HEWLETT PACKARD MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Hewlett Packard shall not be liable for errors contai...

Page 3: ... 2 12 Start up 2 16 Reshipment o 0 2 16 Section III PRINCIPLES OF OPERATION Funct ional descr ipt i on 0 0 3 1 System Clocks 3 3 Memory Address Space 0 0 0 o 3 3 I O Address Space 3 6 Z 80B Microprocessor CPU 3 6 Z 80 SIO 2 Serial lID Controller 3 6 CTC Counter Timer Circuit 0 0 3 19 Interfacing to the BIC 3 19 Memory Interface Circuit MIC 3 24 Regi ster 0 0 0 0 03 24 o MIC Configuration 3 24 1 DM...

Page 4: ...Character Processing 4 11 Automatic Output Separators Appendage 4 12 Transmitting Transparent or Binary Data 4 12 Buffer Flushing 4 12 Prograrrmi ng the Receiver and Transmi tter 4 12 Parity in Transmitted or Received data 4 13 Break Detection 4 13 Handshake Timer 4 14 Additional Options 4 14 Error Handling 4 14 Quoting Character Mode Option 4 17 Condi tional Output Separators Appendage 4 17 Speed...

Page 5: ... Echo CR LF 4 33 28 Output Separator 4 33 31 Additional Options 4 34 32 5ingle Text Termi nator 4 35 33 Card Write Register 4 35 34 5et Port ID 4 36 Control Card Request Code 6 4 36 RTS and WTC Block Definitions 0 4 37 Event Block Description 4 38 Read Status Request Block Definitions 4 40 Identity Information Block Definitions 4 42 Defaul t MUX Configuration 4 42 5ubfunction Assignment Summary 4 ...

Page 6: ......

Page 7: ...he MUX CHANNEL I O is a Hewlett Packard standard defining the physical and electrical characteristics for an I O system consisting of an I O channel an I O channel adapter and I O cards The MUX is one of the I O cards Note that the computer system CPU and memory communicate directly along a Memory Processor Bus MPB I O data to from peripheral devices reaches the CPU memory through the I O channel ...

Page 8: ...27130B I O CARD MEMORY PROCESSOR BUS I o CHANNEL ADAPTER I O CARD I O CHANNEL I O CARD MUX CARD I o DEVICE o o UP TO 6 o DEVICES I O DE VICE Figure 1 1 MUX In a Typical Hewlett Packard Computer System 1 2 ...

Page 9: ...h for mounting RS 232 C panel in HP 19 inch rack cabinets NOTE Bracket has two panel capacity Option 540 Mounting Bracket Part Number 5001 5279 Used for mounting RS 232 C panel on HP 9030A and 9040A computers Option 550 Mounting Bracket Part Number 5001 5280 Used with HP 9000 computer series 500 model 9050A racked in the 92211R cabinet PRODUCT AND PART IDENT FICATION The Product Up to five digits ...

Page 10: ...al supplements available at the nearest Hewlett Packard Sales and Service Office a list of Hewlett Packard Sales and Service Offices is printed at the back of this manual Manuals The Installation Manual supplied with the HP 27130B product and this manual are identified by name and part number Note that this manual is part of the HP 27 132A Technical Reference Package The name part number and publi...

Page 11: ...aming error detection Firmware based self test Optional device handshakes host or device controlled X ON X oFF or host controlled ENQ ACK 16 bit parallel interface to I O channel backplane PHYSICAL CHARACTERISTICS Size 193 04 mm long by 171 45 mm wide by 16 383 mm thick 7 6 by 6 75 by 0 645 inches W ight 283 5 grams 0 625 pound I O Channel Interconnects 80 pin connector J1 Device Interconnects 72 ...

Page 12: ......

Page 13: ...PROM INSTALLATION ICAUTION I SOME OF THE COMPONENTS USED IN THIS PRODUCT ARE SUSCEPTIBLE TO DAMAGE BY STATIC DISCHARGE REFER TO THE SAFETY CONSIDERATIONS INFORMATION AT THE FRONT OF THIS MANUAL BEFORE HANDLING THE CARD OR REMOVING OR REPLACING COMPONENTS The EPROMs are installed in sockets on the MUX card as shown in Figure 2 1 Be sure that they are installed properly and that they have not been e...

Page 14: ...HP 2713GB CPU BIC SID CTC MIC SID CTC EPROM SID CTC EPROM SID JUMPER Figure 2 1 Component and Jumper Locations 2 2 ...

Page 15: ...tion Jumper The Memory Configuration jumper WI is an internally connected 18 pin dual in line package DIP shunt network The jumper configures the two memory sockets U64 and U74 to accomodate dif ferent kinds of EPROMs and static RAMs The pin diagram of WI is shown in Figure 2 2 pin func tions are listed in Table 2 1 16 17 16 15 14 13 12 11 10 2 3 4 6 7 9 Figure 2 2 Memory Configuration Jumper ...

Page 16: ...nstalled only when a 16K byte EPROM is used in socket U64 Position D connects A13 of the address bus to pin 24 A13 of the 16K byte EPROM Installed only when an BK byte EPROM is used in socket U74 Position E connects 5V power to pin 27 VPP of the BK EPROM Installed only when an BK byte static RAM is used in socket U74 POSition F connects WR of the Z BOB CPU to pin 27 WE of the static RAM thus enabl...

Page 17: ...2 2 PERIPHERAL DEVICE INTERFACE Interface between the MUX card and up to eight peripheral devices is via a 72 pin connector J2 to an RS 232 C Connection Unit and from there via eight separate connectors and eight cables to the peripheral devices A connection diagram for the RS 232C panel is shown in Figure 2 4 Connector J2 pin assignments are shown in Table 2 3 Pin assignments for 12 and the RS 23...

Page 18: ... 50 PiN ONE OF EIGHT FEMAlE CONNECTOR J2 ___ RDXlA FEMALE CONNECTOR CHANNELS St kYWN SO 103 AX RDX S DSR 1071 oeD OCD 109 DTRX DTR 108 2 sox RD 104 SGX SG 102 AT5 105 CRX3 CRX2 CTS 105 SHIELD FG 101 Figure 2 4 Connections From MUX to Panel to Device 2 6 ...

Page 19: ...5S 5P HP 27130B Table 2 2 I O Channel Connector J 1 SIGNAL DEFINITION Not used Data Bus Bit 14 Data Bus Bit 12 Ground Data Bus Bit 10 Data Bus Bi t 8 Ground Data Bus Bit 6 Data Bus Bit 4 Ground Data Bus Bi t 2 Data Bus Bit 0 Ground Address Bus Bi t 2 Address Bus Bi t 0 Ground Data Out Bus Primitive Bit 0 Channel End Synchronize Ground Common Clock Ground Burst Request Device Byte My Address Ground...

Page 20: ...14 AD3 Address Bus Bi t 3 B15 AD1 Address Bus Bi t 1 B16 GND Ground B17 UAD Unary Address B18 BP1 Bus Primitive Bi t 1 I B19 CBYT Channel Byte B20 POLL Poll I B21 GND Ground I B22 IOSB I O Strobe B23 GND Ground B24 ARQ Attention Reguest B25 DEND Device End I B26 IFC Interface Clear I I B27 GND Ground I B28 i Not used I B29 I Not used I B30 RES I Not used B31 ISPU I Not used I B32 NMI I Non Maskabl...

Page 21: ... A30 SD3 B B9 RD3 B B31 SD4 A TxD4 A10 RD4 A RxD4 B32 SG4 I I i B33 SD4 B B10 RD4 B I A31 SD5 A TxD5 A12 RDS A RxD5 I A32 SG5 I A33 SD5 B B11 RDS E I B34 SD6 A TxD6 A14 RDS A Rx 6 B35 SG6 I I B36 SD6 B B12 RD6 B I A34 SD7 A TxD7 B15 RD7 A I RxD7 A35 SG7 I A36 SD7 B B13 RD7 B I A17 SDO TxDO A21 SD4 I TxD4 B17 SCO I B21 SC4 I A18 SD1 TxD1 A22 SDS TxD5 B18 SC1 B22 SCS I I I I A19 SD2 TxD2 A23 SDS TxD...

Page 22: ...ector 17 PAIR DOUBLE SHIELDED CABLE exposed shield connection 50mm from 72 pin connector 2 ORN 4 BRN 6 BLU 8 GRN 10 GRY TO MUX J2 1 2 0 iliNica 14 iiBR N 16 BLU o 0 Pair 17 not 0 0 connected th is end 0 0 Figure 2 5 MUX to RS 232C Panel Cable 2 10 ...

Page 23: ...he T tool kit to fabricate your exten sion cable Be careful to match the correct color wire pairs to the correct connector terminal pins on the second connector Repeat the steps on the sheets to connect the second end of the cable to the second connector INSTALLATION ICAUTION I ALWAYS ENSURE THAT POWER TO THE COMPUTER IS OFF BEFORE INSERTING OR REMOVING THE MUX CIRCUIT CARD AND CABLE FAILURE TO DO...

Page 24: ...232 C panel If you have the test hood which exercises more of the card s circuitry connect it to J2 instead of connecting the cable The test hood HP Part Number 0950 1659 can be ordered from CPC ICAUTION I BE SURE TO INSTALL THE DIAGNOSTIC TEST HOOD SO ITS COMPONENT SIDE THE SIDE WITH THE LED MATCHES THE COMPONENT SIDE ON THE 1 1UX CARD DAMAGE TO THE MUX CARD CAN RESULT IF THE COMPONENT SIDES OF T...

Page 25: ...HP 27130B connection Box Mounting Nuts Bracket Mounting Screw Holes Figure 2 6 Option 019 Mounting Bracket for RS 232 Panel 2 13 ...

Page 26: ...all bracket in HP model 9030A or 9040A Computer put hook tab in slot on side edge of computer and fasten with screws Hook Tab Align bracket holes with threaded holes on back of computer Figure 2 7 Option 540 Mounting Bracket for RS 232C Panel 2 14 ...

Page 27: ...top tab in an upper side slot of computer cabinet lift up and put lower tab in lower slot NOTE This bracket needs eight clear side slots in cabinet lower Tab Top Tab figure 2 8 option 550 mounting bracket for rs 232 connection box 2 15 HP 27130B ...

Page 28: ...however refer to Sections V VI and VII for maintenance information replace able parts lists and schematic logic diagrams respectively b If the diagnostic test hood is installed when the self test executes the conditions in step l a should occur plus the LED located on the test hood should light briefly and go out If the LEDs the one mounted on the card and the one on the diagnostic test hood do no...

Page 29: ... dynamic RAM 48K available R5 422 A R5 423 A transmitters and receivers compatible with RS 232 C and CCITT V 28 and I O channel backplane and peripheral device panel frontplane connectors The heart of the l 1UX card is the Z 80B CPU U33 see D24 7 1 which through a program stored in EPROM controls the functions of the card The Backplane Interface Circuit BIC U41 see A14 7 1 is a custom gate array i...

Page 30: ...B The Serial I O circuits 510s U43 U53 U63 and U73 see A42 7 1 and their associated multiplexers receivers and drivers see figure 7 1 sheet 5 provide serial data communication to the frontplane connector 12 3 2 ...

Page 31: ... I IJ m 0 a a J I IJ Z 0 0 SIC 0 0 Z 808 PU DATA 8 AOOR 16 MIC Figure 3 1 MUX Functional Block Diagram 3 3 LOOP BM K MUX HP 27130B SERIAL I o ...

Page 32: ...when this socket is configured for the 16K byte EPROM The address space is from OH to IFFFH when the socket is configured for 4K or 8K byte EPROMs The address space of U74 is fixed between 2000H to 3FFFH The following types of EPROMs can be installed in socket U64 4K by 8 Intel 2732 8K by 8 Intel 2764 16K by 8 Intel 27128 The following types of EPROMs and static RAMs can be installed in socket U74...

Page 33: ...k of the sockets pins 1 2 27 and 28 are not used Tables 3 1 and 3 2 show the settings of WI for different types of EPROMs RAMs 64K FFFFH DFFFH 48K 64K BFFFH DYNAMIC RAM 9FFFH 48K USED 32K 7FFFH 5FFFH 16K 3FFFH 4K 8K EPROM 8K 2K 8K STATIC RAM 1FFFH 4K 8K EPROM OOOOH MEMORY MAP Figure 3 2 Memory Map 3 5 ...

Page 34: ...U74 must 16K 27128 be empty Table 3 2 Memory Configuration Jumper WI Settings for Socket U74 SETTINGS ADDRESS SOCKET SPACE E F G H U74 COM 1ENTS 2000H DON T OPEN OPEN CLOSED 4K x 8 4K byte 2FFFH CARE Intel EPROM 4K configuration I 2000H CLOSED OPEN OPEN CLOSED 8K x 8 8K byte 3FFFH Intel EPROM 8K 2764 configuration 2000H OPEN CLOSED CLOSED OPEN 2K x 8 2K byte 27FFH Hi tachi static RAM 2K configurat...

Page 35: ...s include the stack pointer program counter and two index registers The Z 80B CPU provides the intelligence for the MUX card to function as a preprocessor for the I O devices thus relieving the host computer of a considerable amount of processIng The functions of the Z 80B CPU signals are shown in table 3 4 Z 80 S10 2 Serial 1 0 Controller The MUX card uses four Z 80 S10 2 controller circuits U43 ...

Page 36: ...C 0 Channel 0 1 1 I 0 1 0 0 0 0 DO H eTC 0 Channel 1 1 1 I 0 1 0 0 0 1 D1 H I I eTC 0 Channel 2 1 1 0 I 1 0 0 1 0 D2 H eTC 0 Channel 3 1 1 I 0 1 0 0 1 1 D3 H eTC 1 Channel 0 1 1 I 0 1 0 1 0 0 D4 H I eTC 1 Channel 1 1 1 0 1 0 1 0 1 D5 H eTC 1 Channel 2 1 1 0 1 0 I 1 1 0 D6H eTC 1 Channel 3 1 1 0 1 0 1 1 1 D7 H eTC 2 Channel 0 1 1 0 1 1 0 0 0 DBH eTC 2 Channel 1 1 1 I 0 1 1 0 0 1 D9H eTC 2 Channel 2...

Page 37: ...1 1 0 1 0 0 74 H SID 1 Channel A Control 0 1 1 1 0 1 0 1 75 H SID 1 Channel B Data 0 1 1 1 0 1 1 0 76 H SID 1 Channel B Control I 0 1 1 1 0 1 1 1 77 H SID 2 Channel A Data 0 1 1 1 1 I 0 0 0 78 H SID 2 Channel A Control 0 1 1 1 1 I 0 0 1 79 H SID 2 Channel B Data 0 1 1 1 1 I 0 1 0 7A H SID 2 Channel B Control 0 1 1 1 1 0 1 1 7B H SID 3 Channel A Data 0 I 1 1 1 1 I 1 0 0 7C H SID 3 Channel A Control...

Page 38: ...ut ports Tri state input output active high DO D7 are an 8 bit bidirectional data bus used for data exchanges with memory and I O devices Output active low Indicates that the current machine cycle is the OP code fetch cycle of an instruction execution Tri state output active low Indicates that the address bus holds a valid address for a memory read or write Tri state output active low Indicates th...

Page 39: ...data for the addressed memory or I O device Not used by the MUX card Not used by the MUX card Input active low Indicates to the Z 80B CPU that the addressed memory or I O devices are not ready for a data transfer This signal allows memory or I O devices of any speed to be synchronized to the Z 80B CPU Input active low Generated by I O devices A request will be honored at the end of the current ins...

Page 40: ...U Input active low liD devices and memory use this signal to request control of the CPU address bus data bus and tri state control Signals Output active low Asserted by the CPU to grant the requesting device control of the CPU address bus data bus and tri state control Signals Single phase CMOS level CPU clock input Maximum input frequency is 4 MHz This clock is driven at 3 6864 MHz PHI signal in ...

Page 41: ...rupt vector channel B only I WR3 I Receive parameters and controls I WR4 I Transmit receive mi scellaneous parameters and modes I WRS I Transmit parameters and controls I WR6 Synchronization character or SDLC address field I WR7 Synchronization character or SDLC flag READ REGISTERS FUNCTION RRO Transmit recieve buffer status interrupt status and external status RR1 Special receive condition status...

Page 42: ...gnal a 1 must be written into bit 1 of SIO 0 channel A register 5 On power up reset EN_SED is unasserted i e the transmission lines SDs of the Single ended drivers are in a MARK condition Active HIGH When asserted the RS 422 A differential drivers are enabled Otherwise the transmission lines SD A SD B of the differential drivers are held in a high impedance state To assert the EN_DD Signal a 0 mus...

Page 43: ... parallel to shunt the current and turn off LED The control circuit of the LED is shown in figure 3 3 In order to avoid a large current being sunk by only one of the two SID control signals for a long period of time thus damaging one of the SIOs the time between programming the two SID signals should be kept as short as possible Active LOW When asserted the self test loop back circuits are activat...

Page 44: ...wer up reset LOOP is unasserted i e no loop back If the diagnostic hood is not installed the HOOD_ON signal is pulled to 5V by a 3 3K ohm resistor on the MUX card If the diagnostic hood is installed the state of HOOD_ON is the complement of the state of the HLED signal i e 0 1 1 0 HLED HOOD ON Figure 3 4 shows the circuit used to sense the diagnostic hood This circuit is also used to turn the hood...

Page 45: ... the MIC s DMA controller DMA2 indicates that channel A of SID 0 is ready to transfer data to or from memory By using the MIC s DMA capability channel A of SID 0 channel 0 of the MUX card can support very high data rates On power up reset DMAO is floating Active LOW DMAO is tied to the IRQO input of the MIC When RDYB is programmed as RDYB READY it is a DMA handshake Signal To the MIC s DMA control...

Page 46: ...e diagnostic hood is on To assert the HLED signal a 1 must be be written into bit 7 of SID 1 channel B register 5 On power up reset HLED is unasserted i e the LED on the diagnostic hood is off No modem control lines or modem status inputs are used SIO 0 422 RTSB 5 1 LED SIO 1 RSTB V ON BOARD lED I GND o Figure 3 3 Control Circuit for the MUX Card LED 3 18 ...

Page 47: ...HP 27130B SIO 1 SIO 0 DTRB HLED CTSA 3 3 A A 5V M yS05 HLED HOOO_ON UX CARD DIAGNOSTIC HOOD 220 5V HOOD LED 220 GND Figure 3 4 Diagnostic Hood LED Control Circuit and Hood Sense Circuit 3 19 ...

Page 48: ...CTCs are driven by the 1 84 32 MHz clock PHI_CTC clock generated by U24 see A2l 7 1 The functions of the CTC timer outputs are shown in table 3 7 Note that the CTCs are I O addressable ports to the Z 80B CPU their addresses are defined In table 3 3 Interfacing to the BIC The Backplane Interface Circuit BIC see A14 7 1 provides the half duplex data path to the I O channel backplane As used by the M...

Page 49: ...XCB rate clock 0 2 BRGO SID 0 MUX card channel o baud RXCA TXCA rate clock 0 3 INTERNAL Cause zero Real time clock for count interrupt firmNare to Z 80B CPU 1 0 BRG2 SID 1 MUX card channel 2 baud RXCA TXCA rate clock 1 1 BRG3 SID 1 MUX card channel 3 baud RXCB TXCB rate clock 1 2 BRG4 SID 2 MUX card channel 4 baud RXCA TXCA rate clock 1 3 Not available Counter value can be read polled by Z 80B CPU...

Page 50: ...NPUT NO CH MNEMONIC MNEMONIC FUNCTION 2 0 BRGS SID 2 MUX card channel S baud RXCB TXCB rate clock 2 1 BRG6 SID 3 MUX card channel 6 baud RXCA TXCA rate clock 2 2 ERG SID 3 MUX card channel 7 baud RXCB TXCB rate clock 2 3 Not available Counter value can be read polled by Z 80B CPU 3 22 ...

Page 51: ... Bit 0 Register Address Bit 2 Z 80B Write Asserted by BIC when ready for data transfer Not used Not used BIC Interrupt Non Maskable Interrupt Interface Clear Poll In conjunction with DE determines data bus drivers mode of operation Data Out specifies data bus direction Bus Primitive Bit O With BP1 specifies bus primitive operation Unary Address latches BIC channel address after a PPoN or IFC Addre...

Page 52: ...th an odd byte I O Strobe Data Bus Bit 1 Data Bus Bit 3 Data Bus Bit 5 Data Bus Bit 7 Ground Register Address Bit 1 BIC Select enables the BIC to to read or write Z 80B Read Data Transfer Reguest Reset Attention Reguest 5 V Synchronize Signals that an addressed bus operation is to occur My Address Bus Primitive Bit 1 With EPO specifies bus primitive operation Address Bus Bit 1 Address Bus Bit 3 Ch...

Page 53: ... MIC Configuration The functions of the bits of register 0 read write are as follows Bit 7 DM2 Bit 6 XNT Bit 5 DEND Bits 4 through 0 are not used Selects whether IRQ1 or IRQ2 is the DMA request sensed by DMA channel B If DM2 1 IRQ2 is sensed If DM2 0 IRQ1 is sensed External Interrupt Enable When XNT 1 the I1NT line will be sensed as an interrupt by the MIC interrupt control When this bit 1 the DEN...

Page 54: ...et Register 4 Lower Byte of Transfer Byte Count Channel B Register 4 read write contains the lower byte of the transfer byte count for channel B This register is not affected by reset Register 5 DMA B I O Port Address Register 5 read write contains the DMA B I O port ad dress This register is not affected by reset Register 6 DMA A Upper Byte of Memory Address Register 6 write only contains the upp...

Page 55: ...Byte Count Channel A Register 9 read write contains the lower byte of the transfer byte count for channel A This register is not affected by reset Register A DMA A I O Port Address Register A read write contains the DMA A I O port address This register is not affected by reset Register B Interrupt Vector Register B read write contains interrupt vector information Bits 3 through 7 of register B con...

Page 56: ...pt priority structure is as follows Highest Priority 510 2 Number 0 Channel A 510 2 Number 0 Channel B 510 2 Number 1 Channel A 510 2 Number 1 Channel B 510 2 Number 2 Channel A 510 2 Number 2 Channel B 510 2 Number 3 Channel A 510 2 Number 3 Channel B BIC CTC Number 0 Channel 0 MIC IJ1A Channel A Lowest Priority MIC IJ1A Channel B Wait State Circuits for Interrupt Acknowledge On the MUX card six ...

Page 57: ...rted half a T state after ZIORQ at the rising edge of the following T state At the same time WAIT is also asserted for one full T state to add an additional walt state IORQ follows ZIORQ on the rising edge de asserting edge The timing diagram of the wait state circuit is shown In figure 3 6 DIAGNOSTIC HOOD FOR EXTERNAL LOOP BACK A diagnostic test hood part number 0950 1659 can be ordered and used ...

Page 58: ...7130B NC L I 0 LS 74A PHI eLK _ _ _ R Q _ W T f 5V _ s Q NC 5V D LS74A elK R Q f 5V 422 f V LS32 LS32 ______________ __ RQ __________________ _ ZIORQ M1 Figure 3 5 Wait State Circuit Schematic Diagram 3 30 ...

Page 59: ... HP 27130B TL T1 T2 _ _ _ _ _ _ J _ _ _ 1 TW WAIT STATE GENERATED BY Z 80B CPU AUTOMATICALLY DURING AN INTERRUPT ACKNOWLEDGE CYCLE rw WAIT STATE GENERATED BY WAIT STATE CIRCUIT Figure 3 6 Wait State Circuit Timing Diagram 3 31 ...

Page 60: ...HP 27130B RXDA SIO 0 TXOA 510 0 DIAGNosnC HOOD ___ AI I _ v SD A 511 A A yVV RO 8 50 8 I I 6K 422 1 4W I vv I JV VV 12V 6K RD A GNO Figure 3 7 Diagnostic Test Hood Schematic Diagram 3 32 ...

Page 61: ...e in a high impedance state and they will not affect the single ended drivers hen the single ended drivers are disabled all the SD lines will be In a MARK condition 4 volts and the Dl diodes will be reverse biased The reverse biased Dl will isolate the single ended drivers and let the differential drivers drive the receivers The 511 ohm resistors are used to protect the U9636 single ended drivers ...

Page 62: ......

Page 63: ...rammatically are as follows Number of Data Bits Per Character 7 or 8 Number of Stop Bits lor 2 Transmission Mode asynchronous only in simplex half duplex full duplex or echoplex Parity none odd even 0 or 1 Automatic Detection of Baud Rate by Command baud rate defaults to 9600 Baud rate is programmable from 110 baud to 19 200 baud Break Detection Edit Mode Option to Process Backspace and Line Delet...

Page 64: ...te 0 high byte log channel ID 1 low byte log channel ID I I 2 S BLK F res request code I I L 3 subfunction code I I L 4 po rt ID I I 5 data Ie ngt h high byte 6 data Ie ngt h low byte where log channel I D Assigned by the host for each transaction The card firmware will keep the ID with each transaction until it is completed S bit Used by all non blocked read device data requests and by the last b...

Page 65: ...endent on the type of the request port ID The port ID is the logical port to which the request is directed The mapping of logical port to physical port 0 7 is defaulted as a one to one mapping PID 0 port 0 etc but can be recon figured using WCC SF 34 rite Card Configuration Subfunction 34 A logical port is used to provide compatibility with other CHANNEL I O cards which may not have a simple devic...

Page 66: ...nabled check for backspace or line delete and perform the edit function 7 If the character is a single text terminator and single text termination is enabled terminate the record and make it available to the host If termination stripping is disabled add the character to the buffer If the received character does not match any conditions described in steps 1 through 7 the character now is added to t...

Page 67: ...ter control Y may be used to in terrupt a program from a terminal If fewer than four signal characters are desired the unused characters should be programmed as dupli cates of a lower numbered used character The search for a matching signal character proceeds from Signal 1 to 4 Edit Mode Edit mode may be enabled by setting the Edit Mode option in lrite Card Configuration WCC Subfunction SF 1 Edit ...

Page 68: ...letion character by using the WCC SF 7 The line deletion character causes the card to delete the current line if any If the card is in echoplex mode it will write one backslash then do a carriage return linefeed to indicate that the buffer was deleted Software Handshake with the Device Three software handshakes are available between the host and the device 1 Host controlled ENQ ACK handshake 2 Dev...

Page 69: ...ed by using the WCC SF 18 The default value used is 5 seconds NOTE DO NOT TOGGLE CHARACTER HANDSHAKES TO OFF WHILE WRITE DATA ARE BEING TRANSMITTED IF THE TRANSMITTER INITIATES AN ENQ ACK HANDSHAKE DURING THE DURATION OF THE READ THE ACK CHARACTER FROM THE DEVICE WILL BE TAKEN AS DATA PLACED IN THE DATA BUFFER AND THE TRANSMITTER WILL BE HUNG PENDING A HANDSHAKE TIMEOUT IF ONE IS ENABLED IF THE DE...

Page 70: ... to be used as the text terminator An example of a single text terminator is the carriage return character CR ODH The single text terminator is not added to the buffer unless enabled by WCC SF 8 The character is returned in the event status block and the request status block The Single Text Termination option is enabled by setting the End On Single Text Terminator option in the read device data su...

Page 71: ...nstead you will receive a transmission log of zero length The alert 1 read mode is enabled by setting the alert 1 bit in the data block of the VCC SF 3 When the mode is enabled and there are data on the frontplane and there are no data on the backplane a data available event will be generated immediately In summary the alert 1 read mode has the following characteristics 1 If the backplane has no r...

Page 72: ...H DATA AFTER HAVING RECEIVED A DEVICE X OFF OR NOT YET HAVING RECEIVED AN ACK TO A HOST ENQ Character echoing is enabled by setting the echo bit in the data block of the WCC SF 1 Character echoing may be toggled on or off for the duration of the request by setting the toggle echo bit in the subfunction Echoing is only available for full duplex transmission mode The card will not echo single text t...

Page 73: ...atisfied in total If the S bit is set any data relnaining will be saved for fu ture read requests If the frontplane either has no active receive read or if the frontplane receive record is less than the read request length the firmware will set the down counter to the remaining count needed to satisfy the read The firmware will suspend the read request until the receive record is available for the...

Page 74: ...he control card request with subfunction 3 is used to flush all the queued transmit buffers The current backplane receive buffer is defined to be the record for the next host read If the S bit is set for the host read and if there are any data remaining the remaining data are the current receive buffer If the previous read has the S bit set and there are no remaining data the current backplane buf...

Page 75: ...l it check for any parity The character length specified is the actual data element sent and received The second and third parity options cause the generation and detection of parity for the transmitted and received data respectively by the SIO An additional bit is added to the data element for parity The fourth and fifth parity options clear or set the most significant bit of every character tran...

Page 76: ...l six options are configured by using Write Card Configuration Subfunction 31 WCe SF 31 Error Handling Under normal MUX firmware operation the incoming text is terminated when any receive data error is encountered Furthermore the character causing the error is added to the text record for the host This allows the host to detect the undesirable error condition If the Do Not Terminate Text Record On...

Page 77: ...ll ignore all parity error conditions The character will be processed as if no error had occurred Finally if the lIignore all SIO errorsll option in WCC SF 13 is set all received characters with an error will not be processed However the error bit in the termination code will be set to indicate that an er ror had occurred and that characters have been discarded Figure 4 2 is a flow chart showing h...

Page 78: ...N THE STATUS CODE SIT ERROR BIT IN THE TERMINATION CODE REPLACE RECENED CHARACTER WITH THE REPLACEMENT CHARACTER CONTINUE NORMAL RX PROCESSING ___ EXIT IGNORE CHARACTER TERMINATE THE CURRENT RX RECEIVE FIGURE 4 2 ERROR HANDLING FLOW CHART 4 16 ...

Page 79: ...ace of the record separator If the Automatic Output Separators Appendage option IS enabled the output separators are also added to the end of each message Speed Sense Mode The Speed Sense mode initiated by Control Card CC Subfunction 6 puts the card in a mode where the baud rate of incoming data is sensed and the channel configured accordingly The firmware waits for a start bit and in synchronous ...

Page 80: ...ted the card is left disabled indicating that self test failed The following tests are performed by self test ROM test To ensure that no bits have changed on the ROM EPROM a cyclic redundancy check is done using the polynomial X 16 X 2 X 1 The test is performed in 4K segments to ensure accuracy of the CRe RAM test RAM is checked for both stuck at O and stuck at 1 conditions and address decoder fai...

Page 81: ...ot set and the Z80 is Halted The following time line illustrates the host card interactions during the self test sequence Host to sends card DCl or assertsl RES after a power on Teach card PA Wait time t2 or poll PST where t1 t2 t 1 1 0 second Card Self test begun Successful Set PST Turn off lED Unsuccessful Hal t Z80 t2 3 seconds if RES or 15 seconds if DCl DEN may be less CONNECT LOGICAL CHANNEL...

Page 82: ...ACK Handshake paragraph Write Device Data Request Code 2 Subfunction code automatic output separators appendage Read Card Information Request Code 4 For the read card information request the residue count in the read request status block will reflect the number of bytes of information not returned in the request This always will be non zero when the requested data transfer lengths are not large en...

Page 83: ...e of any receive data terminated or not on the MUX for the indicated port Received data exists on either the backplane or frontplane if the returned byte is non zero The data block returns the following byte 0 data on frontplane or backplane Subfunction 250 Get Card RAM The uppermost 16K bytes of card RAM memory is sent to the host in the data block The other 32K bytes of RAM are not used by the M...

Page 84: ...be cleared each time it is read Write Card Configuration Request Code 5 NOTE The firmware will perform parameter validation where possible Every write card configuration request data transfer length must match exactly the length specified for the request otherwise the illegal configuration pa rameter length error will be returned in the read request status block If the data transfer length is not ...

Page 85: ...ng to each subfunction code This subfunction allows one call to configure everything instead of calling each individual item After the initial configuration a particular item can be changed as needed Note that if you use this subfunction every item must be specified with new values The default values or the previous values that were specified will be set to the new values given The data block is d...

Page 86: ... 27 device X OFF character 28 host ENQ character 29 h09t ACK character 30 host ENQ ACK counter 31 reserved 32 reserved 33 a single text terminator character 34 number of output separators 35 1st output 36 2nd output 37 reserved 38 reserved 39 reserved 40 reserved 41 reserved separator separator 42 additional options character character or or for echoing CR LF null null 43 replacement character for...

Page 87: ...0 1st single text terminator character 51 2nd single text terminator character 52 3rd single text terminator character 53 4th single text terminator character 54 5th single text terminator character 55 6th single text terminator character 56 7th single text terminator character 57 8th single text terminator character 58 signal character 3 59 signal character 4 Val idation Data length must be 58 or...

Page 88: ...haracter handshake Validation If the echo bit is set the transmission mode must be full duplex The transmission mode must be programmed first before setting the read option Subfunction 2 End On Count Length Data block 7 6 5 4 3 2 1 0 byte 0 high byte end on count length l 1 low byte end on count length Validation none 4 26 ...

Page 89: ... range 2 through 4 inclusive The transmission mode must be set before setting the read option Note that the echo bit will be reset if the transmis sion mode is not full duplex Subfunction 6 Backspace Character The character specified in the data block will be used as the backspace character for the edit mode Validation none Subfunction 7 Line Delete Character The character specified in the data bl...

Page 90: ...er Options Data block byte Validation none 0 backspace echo 1 backspace ove r wr i t e 2 backspace only han ds hake time r is for X ON X OFF or ENQ timer 1 0 respectively reserved rese rved reserved strip single text terminators reserved 4 28 ...

Page 91: ...es out _______ echo CR LF for a specified single text terminator Validation none Subfunction 10 Baud Rate Data block byte 0 I LbaUd rate 0 reserved 9 1200 baud 1 reserved 10 reserved 2 reserved 11 2400 3 110 12 reserved 4 134 5 13 4800 5 150 14 reserved 6 300 15 9600 7 600 16 19200 8 reserved 17 31 reserved Validation The value must be within the range 0 through 16 inclusive 4 29 ...

Page 92: ...rved 2 reserved 2 7 data bits 3 8 data bits Validation The value must be within the range 0 through 3 inclusive Subfunction 12 Number Of Stop Bits Data block I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I byte 0 y 0 1 stop bit 1 reserved 2 2 Validation The value must be within the range of 0 through 2 inclusive 4 30 ...

Page 93: ...n 18 Character Handshake Timer Subfunction 18 sets the handshake timer in incre ments of 1 second The timer can be programmed from 0 to 255 seconds The timer is used for either the ENQIACK or the device X ON X OFF handshake Because there is only one timer per port the handshake for which the timer is used is selected by wee SF 8 If timer selected by wce SF 8 is not the handshake enabled by wee SF ...

Page 94: ...t Data block byte 0 transmit buffer is empty reserved signal character 1 Signal character 2 signal character 3 signal character 4 I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I byte 1 LLreserved character handshake timeout reserved reserved reserved reserved reserved reserved Validation None The data are not checked 4 32 ...

Page 95: ...25 Host ENQ ACK Pacing Counter Data block byte 0 the number of characters to transmit before sending an ENQ and waiting for an ACK count should be 1 to 225 Validation One byte must be given HP 27130B Subfunction 27 Single Text Terminator for Echoing CR LF Anyone of the single text terminator characters may be specified to cause the echoing of the CR LF characters However only one charac ter may be...

Page 96: ...e text record on receive data error enable signal character detection insert a null character into the receive buffer when a break is detected replacement character for the bad incoming character quoting character record separator character to invoke sending the output separators signal character 1 signal character 2 quotable single text terminator signal character 3 byte 8 signal character 4 Vali...

Page 97: ...text terminator Validation From one to eight characters may be specified Subfunction 33 Card Write Register This subfunction is used for on line diagnostics capability Data Block I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 I byte 0 reserved differential drivers off _____single ended drivers on _____loop back hood LED on ____ Sel f t es t mode on card LED off reserved reserved 7 6 5 4 3 2 1 0 byte 1 0 1 0 1 0 ...

Page 98: ... logical port ID except that it should not duplicate any other ID Validation The data must be between 0 and 7 inclusive Control Card Request Code 6 See the paragraph Buffer Flushing for additional details on this request code A summary is shown below SUBFUNCTION DESCRIPTION a 1 2 3 4 5 6 7 No operation Flush the current receive buffer Flush all the queued receive buffers Flush all the queued trans...

Page 99: ... RTS description Nothing to do The LCN field is not used Swi t ch tot he transaction given in the LCN field 1 0 WTC description Not used Resume the transaction given in the LCN field 2 Terminate the data Terminate the data 3 4 transfer for the transaction given in the LCN field Abort the trans action given in the TID field Event sensed The event block as defined below is transfer for the transacti...

Page 100: ...d 1 data message received Message length and type are given in the information field byte 3 4 5 6 7 6 5 4 3 2 1 0 high byte length I I low byte length I I I I no t used E message type I I t ext term for message type 1 message type field 1 text terminated on single text terminator The text terminator which terminated the message is given in byte 6 4 text terminated by count 5 text terminated by par...

Page 101: ...is record contains an error Parity Error PE Framing Error FE Overrun Error OV codes continued break received from the device transmit buffer is empty signal character 1 received signal character 2 received signal character 3 received signal character 4 received rese rved character handshake timeout 11 to 253 reserved 254 speed sense completed 7 6 5 4 3 2 1 0 byte 3 where baud rate is as defined ba...

Page 102: ...quest status I I 1 length of data transfer 2 I 3 length of data remaining in l 4 e urrent rec 0 rd for the read I I 5 not used E message type 6 text terminator for me s s type 1 card dependent request status field 0 no error 1 illegal subfunction 2 illegal configuration parameter values 3 illegal configuration parameter length Amount of useful information END here for all control requests Amount o...

Page 103: ... early termination initiated by the host For example if the host started a host read request of 200 bytes and the card is able to send 200 bytes the card will return the length as 200 even if the host invoked END to terminate the transfer early message type field text terminated on single text terminator The text terminator which terminated the message is given in byte 6 4 text terminated by count...

Page 104: ...rts 1 7 I I 6 max request s port 1 2 I I I I I 7 maximum guaranteed 8 data blocking size 252 END MPX 1 for in channel multiplexing MOD 2 for both byte and word mode data transfers DEFAULT MUX CONFIGURATION Upon a reset or power up condition the MUX will be set to the configuration states defined below enable software handshake no edit mode disabled echoing disabled terminate on single text termina...

Page 105: ... X OFF handshake disabled host ENQ ACK handshake disabled baud rate 9600 character length 8 bits character number of stop bits 1 pari ty none host ENQ ACK timer 5 seconds host interrupt mask all cleared to disable interrupts host X ON character DC1 host X OFF character DC3 device X ON character DC1 device X OFF character DC3 single text terminator for echoing CR LF CR host ENG character ENQ host A...

Page 106: ...er 2 OFF hex signal character 3 OFF hex signal character 4 OFF hex quotable single text terminator character EOT Control D number of single text terminators 1 single text terminator character CR SUBFUNCTION ASSIGNMENT SUMMARY A summary of all subfunction assignments is contained in the following paragraphs Read Device Data SUBFUNCTION bi t 7 toggle character handshake bi t 6 toggle signal characte...

Page 107: ...us Write Card Configuration SUBFUNCTION 0 configure subfunct ions 1 through 32 configure the read option 2 end on count length 3 configure alert 1 mode 4 not used 5 transmission mode 6 backspace character 7 line delete character 8 other options 9 device handshake option 10 baud rate 11 character length 12 number of stop bits 13 parity 14 not used 15 not used 16 not used 17 not used 18 character ha...

Page 108: ...ng CR LF 28 output separator 29 not used 30 not used 31 additional options 32 single text terminator 33 card write register 34 set port ID o no operation flush the current receive buffer 2 flush all the gueued receive buffers 3 flush all the gueued transmit buffers 4 host initiated frontplane receive text termination 5 force restart of transmitter if waiting for handshake 6 enter speed sense mode ...

Page 109: ...au tomatically at power on or only when specifically invoked by you 4 Turn on computer system power 5 When the self test executes the LED located on the test hood and the LED located on the MUX card both should light briefly and go out if the card passed self test If the LEDs do not light at all the card is defective If the LEDs stay lit the card did not pass self test If desired isolation to a de...

Page 110: ......

Page 111: ...Packard part number 3 Part number check digit CD 4 Total quantity QTY 5 Description of the part 6 A manufacturer s five digit code number of a typical manufacturer of the part Refer to Table 6 2 for a cross reference of the manufacturers 7 The manufacturer s part number ORDERING INFOR s1A TION To order either replacement parts or to obtain information on parts address the order or inquiry to the n...

Page 112: ...ct identification information sup plied in Section 2 2 Description and function of the part 3 QuantitYrequired PARTS NOT IN PARTS LIST The replaceable parts listed in Table 6 1 only has parts on the printed circuit assembly Other parts supplied with the 27130B such as cables RS 232 C panel EPROMS cable kit and optional brackets have their part numbers listed in Section I 6 2 ...

Page 113: ...A 125V NTD 281X 093 FUSE SA 125V NTD 281X 093 FUSE 5A 125V NT 281X 093 CONN POST TYPE 100 PIN SPCG 80 CONT CONN HDR 72 PIN CONNECTOR 16 PIN tI POST TYPE CONN HDR 40 PIN CONNECTOR 16 PIN tI POST TYPE TRANSISTOR NPN SI TO 18 PD 360MW TRANSISTOR PNP SI PD 20 OMW FT 50 OMHZ RESISTOR 5 11K IX 125W F TC 0 l00 NETWORK RES 10 SIP3 3K OHM X 9 NETWORK RES I O SIP I OK OHM X 9 RESISTOR 422 I r 125W F TC 0 10...

Page 114: ...TTL LINE DRVR DUAL BURNIN 18113 1425 IC MUXR DATA SEl TTL LS 2 TO l LINF QUAD ICD 75174 DR IVER ICD 75174 DRIveR IC RCVR TTL LS LINE RCVR QUAD 2 INP IC DRVR TTl LINE DRVR DUAL IC DRVR TTL LINE DRVR DUAL BURNIN 1818 1425 BURNIN 1818 1425 BURNIN 1818 1425 SOCKET IC 18 CONT DIP DIP SL DR NTWI SHUNT P RGM SOCKr T IC 40 CONT DIP DIP Sl DR SOCKET Ie 14 CONT DIP DIP SlDR SI T 64 PIN SQ SOCKET IC 28 CONT ...

Page 115: ...any Mi lwaukee Wi 53204 01295 Texas Instruments Inc Dallas Tx 75222 Semiconductor Components Div 07263 Fairchild Semiconductor Div Mountain View Ca 94042 24546 Corning Glass Works Bradford Bradford Pa 16701 28480 Hewlett Packard Co Palo Alto Ca 93404 Corporate HQ 56289 Sprague Electric Co North Adams Ma 01247 6 5 ...

Page 116: ...U41 U43 U55 U54 U65 I U53 U51 2 I U75 t I IE U85 U64 U63 U61 U95 i I IE U105 U74 U73 U71 2 U115 12 I 12 J 2 W1X1 U84 U83 U82 I U125 R18 U92 CO N 2 U97 12 12 U95 a II U96 U102 II u CR4 0 F1 F2 F3 FIGURE 6 1 HP 27130B PARTS LOCATION DIAGRAM 6 6 ...

Page 117: ...SCHEMATIC DIAGRAMS IF INTRODUCTION This section contains schematic logic diagrams for the MUX card 7 1 7 2 ...

Page 118: ...S Dt7 llttl j SOl III Se RI 8 X 8 r 5V 3 3K 8 RI 6 j 5 __ D I ff EN I I I I SL E SN D 5 5 5 8 OJ EN I 2UI 121 r ce CC 2 ILS24 3 5 7 9 8 8 2 VlJ 1 04 2 19831 1 f1 r I1 iT t V i l i1 Jl li 3 il t 8 RI 7 8 r SCO 8 t2 I 21 S1 tlU VCC Yee 12 SCt iT t 2 V I J IW I 5LE D I 1 V u9 4 2 i 838 t3 t t j RI 5 8 r c 5 U8 4 U8 3 I l5157 3 t t t t d2 IT 1 9________ 21 U 2 d f vee vce 12 AIW I SLEW no vUYI 03 2 i ...

Page 119: ... UID AS IU IU IU IUJ IP IP DOUt UD It U S L DU Dst 05 00 01 D n 0 PI 0 07 HP 27130B U41 BI C AST SULIY 8R DUD onT DE llDOI 11001 1100 11003 IlDo 11005 IlDO BlD01 11001 alODI 110010 BIOOII 110012 810013 810014 II OOts AR IUO 11 15 U23 jt J I r W 13 L_I IE I U22 I S2U I I I I V 15 L _ _ _j l Ne u I o U 2 I I IV II 55 21 51 57 27 51 12 1 14 1 11 16 EIIIIN I It II lm U12 HI l IU L j iillCI 12 I DUll I...

Page 120: ... II 1 I PIOI ICEZ I I z I CE 1111 L _ _________ CE Itll ICEI k II 2 n II I mil n II I 1 EPADI ICC liD liD S fu 54 IC H C UD I _ IU S R I DIIT t _ I a I I _ E S E I SEL 1 1 _ O A J DIED IC n EPRII SDCI 111 3 n I _lPtiOl ZJ III 4 III P v H v T II 5 S rl v H II I 113124 vee liZ III 1211 110 1111 II IZZ 1231 I III IZI 15 131 I 1 1 13 lSI IZ III II 111 II III DE 1211 Hl IISI n Hl I 5 Hl__ J 1111 DI r H...

Page 121: ...11 0A 1 7 15 ___j__t_ JE5t If RDYA ONC ATSA NC DIAA r 6 NC 1 7 __l__t_ I O 1I ADY8 r HC RIS6 r IfC DUB r Ne A B Q C RXD2 ______ 1Q C IO 1 t t r l 1 t_ I _ 1_t_ __I__ _ll 0 t_ I _ _t_ o07 __IH_ __l_ ___j __i_ _ 7D1 j I _ _t_ H o07 I _ _t_ H 7 t j _ __l_ _ _ _ _j_ c o E r I O r H j 51 1 0 t t 4 _I_ _I_ _t _I_ _ _ r t_l_ t r1 t E 5 I 1_t_ __t t_r_ _ _I_ t_r_ _t_ _H _I_ _ t_r__ _ _I_1_t_ _t _ 4 I _ _ ...

Page 122: ...LSO 3 CLOSE JUMPER AFTER Ole CLOSE JUMPER FOR EPROItS SIGMA TURE ANALYSIS IHICH AVE REATER THAN U33 TEST S 250NS ACCESS TIlE r S iJ 8 AO r LSOB CII RESEI 2 II 041 C3I 24 AESET VOO 110 21 _ IIILU C3t UJT 12 JNT II 20 UOAl CII ClI 17 IIIT 10111 19 MAU E3I CU lUI UEI NC 83 IUS I U3 4 9 o I 25 HAL I cn 0 8USRI 8USli U U U A7 I O ABOA IUS C4I CLOSE JUIPER HlEA Af SH i NC AO U lIt ADOR IUS CII SI NlJUA ...

Search results

Summary of Contents for 271308

Reviews:

Related manuals for 271308

Brands by name

Popular brands

HP 271308, Technical Reference Manual

Search results

Summary of Contents for 271308

Reviews:

Related manuals for 271308

Brands by name

Popular brands