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HP 13220, Technical Information

The HP 13220 is a powerful and versatile device that offers outstanding performance for a wide range of technical applications. With our free manual download available on manualshive.com, you can quickly access detailed technical information, enabling you to maximize your productivity and make the most of this exceptional product.

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Summary of Contents for 13220

Page 1: ...Pf c T Mod u 1e Manual Part No 13220 91087 REVISED JAN 4 B2 DATA TERMINAL TECHNICAL INFORMATION HEWLETT PACKARD Printed in U S A ...

Page 2: ...liable for errors contained herein or for incidental or con f quf n t i al dat aqE s in c nn ction with th fUl nis hinq E l for Manc or use of this Material This dOCUMent contains proprietary inforMation which is protected by cop Y7 i q h t All r i I h t i f r f f r vE d N P a t 0 f t h i cI 0 c lJ M n t JII a y bf photocopied or reproduced without the prior written consent of Hewlett Pac k r d C ...

Page 3: ... of which 32K are used for COMplete terMinal operation 8K of ROM optional with integral printer The video control section provides all tiMing signals for driving the sweep circuitry and video logic as well as perforMing direct MeMory access CDMA of display data A detailed description of the operation of each of these sections follows i n ec t ion 3 0 2 0 OPERATING PARAMETERS A SUMMary of operating...

Page 4: ... product level I I I I I I Failure Rate 3 71 percent per 1000 hours I Table 3 0 Power Supply RequireMents Measured At 5 Unless Otherwise Specified I 16 Volt Supply 12 Volt Supply 5 Volt Supply I 12 Volt Supply I ill 0 MA 200 MA 2 0 A I SO MA I I NOT APPLICABLE I I I I I I I I I I I 115 volts ac I 220 volts ae I I I I I A I A I I I I I NOT APPL ICABL E I NOT APPLICABLE I ...

Page 5: ...PRINTER PWI ON FAIL WRITE Ai DATA DATA 1 DATA 2 DATA 5 DATA 4 DATA S DATA 6 DATA 7 GND PINT AO SV SV SV SV GND GND GND GNU GND Signal I Description I PRINTER Negative True Printer Strobe Negative True Power On Failing Negative True Write signal Negative True Fun tion select bit 1 LSB Negative True Data MSB Negative True Data Set printer contrast Negative True Printer Interrupt Negative True Functi...

Page 6: ...ry TerMinal I I _ I _ _ _ _ _ _ I I J 3 1 I I __ _ __ __ I I Pin 1 HLFBRT I I 2 I 3 RETURN I _ _ _ _ I I 4 FUL L BI T 5 RETURN I 6 RETURN I I I J iJ f ifi rf I 8 I HORDR I I _ 1 J4 I I I I I I Pin 1 2 3 4 s 6 7 B 9 1 1 1 12 EYO KEYj KEY2 KEY I EY4 KEYS KEY6 KEYACT GNI BELL Sv SWEEP Negative true Half Bright Video N C Return for half bright twisted pair Negative true Full Bright Video Return for Vi...

Page 7: ...t urn 6 GND P w r Return J DeDi Rat S lect 23 8 Nit 9 RD R c f d V d l clti 3 10 Nit 1 i Clf dr To Send 5 12 DM Di l ta S t Rei ld y 6 13 N C 14 Nit 1S SG Si na 1 Gr 0 und 7 16 NIt j J N C 18 OCR1 Rinq Ind i cator 2 j 9 1 V 12V Pod Power 0 1 V 1 Pod Power 21 SD Tr HlSMl t t d Data 2 RS r eqllest To Send 4 TR Ready 20 4 Nit 25 N C 26 NIt 27 N C 8 N C 29 N C 3 Nit 31 N C 3 GND Return 33 SHIEL l Shi ...

Page 8: ...upt service routine The ZBOA also responds to a bus request signal NBUSREQ allowing the CRTC control of the systeM b u es At power up or reset the ZaOA begins executing instructions frOM prograM MeMory beginning at address OOOOH A routine is executed which initializes variables and devices according to inforMation contained in non volatile MeM ry CMOS and perforMS a self test of ROM and RAM If an ...

Page 9: ...e to COMpensate for the unique tiMing of the 6500 series devices The SY6551 is selected by the rising edge of SELDC which is inverted frOM U24 the 1 of 8 decoder The addresses of the SY6SS1 U613 are AO A7H The status inputs of the SY6SSl produce undesirable results and therefore are forced to their active low states while the necessary status signals are routed through another port RS 232 line dri...

Page 10: ...ive high 12V Upon receipt of a character frOM datacoMM the SY6SS1 generates an interrupt signal NINT to the lBOA This causes the ZaOA to branch to the datacoMM interrupt service routine which reads the SY6S51 status clearing the interrupt and if no errors are present inputs th character and places it into the datacoMM buffer in RAM Characters for which errors parity fraMing or overrun are present ...

Page 11: ...nter control is specified by perforMing a write operation to the printer with address lines TAO and TA1 and data lines TDO TD7 selecting the particular function Printer status is read back frOM the printer on the upper half of U1S which is enabled for read operations frOM the printer port The presence of the printer is detected by reading status frOM the printer and checking data bit TU1 TU1 will ...

Page 12: ... I CRTC Map I I U68 I 4BK I _ M M _ _ I CO OH I DynaMic I AM I I buffers I I display MeMory I I stack I I systeM variables I I I I ZDO ZDt ZD2 ZD3 ZD4 IDS ID6 ID7 I I U41 U42 U43 U44 US1 US2 US3 US4 I 64K R a d on 1y M Mor y As can be seen frOM the MeMory Map 4B K of address space has been allocated for read onlY MeMory ROM This MeMory contains the ZaOA prograMS which controls the terMinal operati...

Page 13: ... ZUOA I EAD WI ITE A Z80A access to RAM is initiated by lowering the TNMREQ signal at an address location between COOOH and FFFFH RAM address range Prior to TNMREQ going low the output of U77 would be high causing l s to be shifted through the shift register U510 by DRCX As TNMREQ goes low TNRFSH is high the output of U77 goes low also As the clock occurs O s are shifted through the shift register...

Page 14: ...stating its address and control lines and activating the NBUSAK line signalling that the bus is available and will reMain so until NBUSREQ is raised The NBUSAK signal is inverted and buffered by U79 to provide both IBUSAK active high and TNBUSAK active low buffered These signals are used to tristate the address and control buffers U47 US and US11 and enable the video subsysteM for DMA action TBUSA...

Page 15: ...te Although the shift register load signal is enabled four character tiMes before active video the CRTC holds the starting address until active video and then increMents it during active video In addition the data is not clocked into the line buffer until the line buffer clock transitions low during active video On the last scan line of a character row scan line 14 the CRTC lowers the LBRE line bu...

Page 16: ... again During this tiMe the beaM is also being swept vertically The COMbination of these two produces the display raster As the beaM reaches the bottOM of the display a vertical sync signal is sent to the sweep causing the beaM to retrace frOM the bOttOM right to the top left corner In this Manner the CRT display is written 60 tiMes per second when configured at 60 Hz or optionally SO tiMes per se...

Page 17: ...tical blank and vertical sync signals and the fraMe rate TABLE b O FraMe TiMing FraM Rat 60 Hz I SO Hz Delay after v blank to v sync 1 scan lines 0 v sync width I scan lines 19 64 v blank duration I scan lines 25 1 08 Total i scan lines per fraMe 415 Display MeMory addressing Section 3 2 2 describes how the eRTC perforMS DMA to load the line buffers with character and enhanceMent data for display ...

Page 18: ...al through the systeM status port Character display At any given tiMe the characters for the current row being displayed are held in the recirculating line buffer U39 The character codes output frOM this line buffer are resynchronized to the character clock through the octal latch U310 frOM which they are sent to the character ROM U311 This ROM contains the dot pattern for each scan line of each e...

Page 19: ...ded into the MSB The QD output of U313 goes to the character Multiplexor U213 This Multiplexor selects one of several inputs to gate to the dot streaM For a norMal scan not half shift the Multiplexor select inputs will be 101 C input is Most significant selecting the DS input As the dots are loaded into the shift register the first dot which is high appears on the DS input of the Multiplexor and i...

Page 20: ...or standard characters The MOst significant output is loaded into both the A and B inputs of shift register U314 at the saMe tiMe as the least significant seven bits Thu th MSB i cop i E d i n hift reg i ter U3t4 The l eMaining dots are brought frOM the QC output of U313 into the serial inputs of U314 thereby forMing a nine bit shift register with U312 U313 and U314 The QB output frOM U314 is then...

Page 21: ... d 1 W Th i i c a u i e i t h co dot s t c M t 0 b act i V f 0 l the 13 can l i n t 1 0 F the c h i l iH t H P 0 sit i n l n whie h t h CU l 0 T 1 i s I n f f of C t t his 0 I s t hE cur 0 r wit h the character in the cell a non Mdestructive cursor If the copy bit c i r c u i t i act i v how v H the D 0 f D 5 i n put 0 f t h o C h a r a c t EH M U 1 tip 1 x0 r i H t j t 11 E c t 01 d T1 E E i nput...

Page 22: ...rH i s e tin the f i r t chi r a c t r po s t ion f a c h r w H i t EN6 as d SC r i b d a b ve of 0 r MS t h M 0 S t s i qn i fie ant add r s bit f 0 l a n BI b Yt e c h i f act f l R M As a character is latched into U31 0 six of the seven enhanceMent bits a l o 1 a c h f d i n t t h h x 1a t c h U I The s f t E n han c E Mf n t bit i s latched at the saMe tiMe by LCGAX into Ut8 At this tiMe EN6 i...

Page 23: ...n the halfbriqht attribute is activated the dot inforMation is inhibited frOM th NFUI I BRT output whic h Jiv s full intf n ity c hal ac t r LJ1tc pin b by pulling Ut12 pin 4 low and is enabled through U110 pin 8 which I d tI act i V E I W d tin f Ma t i n n NI IAl FHI T t t he SWE f p ENO ClF l I NE Th reMi lininq nhanCE Mf nt bit E NS pel fOrMS the f nd of line function When set this bit causes ...

Page 24: ...NK and disable NCUR VBlANK and DISPOFF also blank the display in a siMilar fashion The last part of the video section to consider is the enhanceMent off circuit which allows the enhanceMent latches to be disabled The ZaOA sets the ENHOFF signal output froM U26 which is latched by the RECIRC signal into U17 The Q output U17 pin S is gated through U27 to clear U210 while the Q output Ui7 pin 6 clear...

Page 25: ...TS CUR I ISHI DISPOFF DM DRCX The 1 84 MHz datacoMM chip clock The 3 68 MHz l80A clock Sets the video fraMe rate low SO Hz video dot streaM after dot stretch con nE c t i 0 n t t hE b c t tel y I tel MinaI for CMOS backup during power off U t p J t s i 9 n a 1 t d l i vet IH lo yb h ll d bt 11 inhibits the ALPHA dot streaM frOM being sent to the sweep circuitry alternates at the blinkrate for blin...

Page 26: ...video attribute keyboard row coluMn scan outputs delayed line buffer clock line buffer clock 13220 91087 25 Rev JAN 04 82 delayed latch character generator address latch character generator address load video shift register RAM data outputs selects between row and clouMn address for dynaMic RAM select blink attribute request bus control for DMA colUMn address strobe for RAM enable CMOS for read wr...

Page 27: ...e select cLock ModeM display latch clock RAM output latch non Maskahle interrupt video power fail signal frOM power supply printer select signal row address strobe for dynaMic RAMs power on reset driver A power on reset drivel B datacoMM port select systeM status port select optional control driver 1 datacoMM optiorhll control r ece iv r i datacoMM printer i terrupt status COMMon pullup resistor r...

Page 28: ...its 0 15 bus acknowledge ZaOA tristate buffered data bus active low bus acknowledge zaOA MeMory request MeMory or 1 0 read select dynaMic RAM refresh active MeMory or lID write select terMinal ready datacoMM select underline attribute active on scan line 13 indicates scan line for underline or cursor display vertical blank signal vertical synchronization signal 1 3220 9108 7 27 Rev JAN 4 82 charac...

Page 29: ......

Page 30: ... aJ r o n CJ D G 0 D 3 PROCESSOR AND CONTROL APDRESS BUS MEMORY ROM RAM r l I O DECODE AND BUF F R 1 1TDATA BUS _ PRJNlD I O KErRET KEXSCAN BELL EROM HOST TO HOST DATACOMM i Fl ure 1 VIDEO SUBSYSTEM Blocl DiagraM JAN 04 B2 ...

Page 31: ...ev _ i I 6 ZQ3l 3 Q p cx _ CTl ili t 8U SA l n1 l 7 5V L l _ 7C l prk U410 10 LV5RX 1 502 Silz Q w II IS pL II q I 2 H I 51 G 4D 1 Q r o 3 pF 1 1115 LSZ s U14 m I L S175 15L l ZI III I l 3 LI II 1 1 J f W3 1 U75 L 6ADEl Ll cDEL Vc 2 C_ j 1 I Cl tJ T 1 H c Xh ______ _ 3 I UII2 13 Uti I u 3 TAI 3 bJ g Q 1 4 S ___ _ TAIl T 7 S tr XS ______ L c 1I 3 1 500 LSOO 11 71 SOO _ C RC _ _ ___ IZ 13 Ls32 l v _...

Page 32: ...__ _ _v_ _ _ _____t_S_v_ _ _ ____ 1111 I 2 1 1 v TA7 TA7 NIO I JllMPE RS SHOWN IN STJ CON FIG 2 SPARES uZI4 rJ 1 t 7411 SO 4 l In 4 A PULl UP 5V IK R f l RESETA 7 T UIDII a OP I D QD 114D J I A e c 0 3 5 11 ZlIA t t1 I Hi KEVBOARI ISO I2 lU7 1 100 1 R40 T470pI VC38 I 4t NRE5ET8 z t4C tI4c 2 1A IK R31 511 3 l 1 5v 470 R 7 Etr 0 e 3 8 MH II u 2 LCL LS7 13 iIO L51 e TPS NCMOSIl Q 8 Mt U37 lilli TNRD ...

Page 33: ...IT W U TNRD CC f lOATA IN a 1 TNWR ZOATA OUT T1 1 2 rw I I I _____272 NS t X 110 ESS l I I I I I I i I I 1 3 J W I 1 J1 I I I Tl 1 3 I X I i I 1 2 Tl I X 1 r 1 I I 1 I J l J I J J I AUTOI IFITICfLLY INSERTED IT STATE FIGURE 4 0 Z80A I O TIMING Figure 4 I O TiMing DiagraM JAN 04 82 13220 91087 ...

Page 34: ... i I I I I i I I T4 Tt I REFRESH ADDR I ROM DATA f I UUIX VA4ID DATA fll I I Tl T2 I I I I I NWAIT 1 ___ _ R_A e _l u l t u_ X r i n_ _n_nj X r ________m 1 i I I I I MEMORY TNRD READ I I I I I I i I I j I SMEM0 SMEM5 I II I i f I I ROM DATA VALID DATA FIGURE 5 0 Z80A ROM TIMING Fi Ul e S ROM TiMing DiagraM JAN 04 82 13220 91087 ...

Page 35: ...l D7 READ UH o TNWR OJ US II liO N l D 2 D7 WRITE lSOA ut8 YI fO 2 1 4 G j II II I I I I II II II I I I I TI II II II j IDEo I ViDEO I 3 4 5 4 5 7 8 9 I I I i II I I ______________ I I _______________ U II II II II II II I I II II II II 1 II U II II I I I I I I NVALID CHAR 3 lNvAL ICO CHAR I r AMS TRI TATE RA S T ISTATt I I T2 T3 II II II FIGURE 6 0 RAM TIMING RAM TiMing DiagraM JAN 04 82 13220 91...

Page 36: ... _ IN R IHLFB_R_T_J_Ul_IN_E_________________ L__________________ ___ NtuR NU LlNE ALPIfA I IBLANK vBLANK UHE j L INE 3 If II I 1 s I I 1 1 I 1 LJ I I I I I I lJ I 1_ _ _ 1 _ _ IJ 1 5 1 1 1 l r BLANKiNG C H AR 1 _r I I c HAR 80 VIDEO 4X MAG Nin ATION FIGURE 7 0 VIDEO L11 JE RATE TIMING 1 r BLANKIN6 Figure 7 Video Line Rate TiMing DiagraM JAN 04 B2 13220 91087 ...

Page 37: ... UX SEL A H5 11 CH MWI Sf L B I DSET II NGURSOR I I CH MU x OLJr NOF MAlJ L II__ 1 1IIL I 1_ 1I 1 I II CI MUX our HS n1 J ___ 11 II II II II CH MUX oU1 CLDSET IL LI_ LI I _______ 11 11 II II II II I I I I II LL II L L II II I I II II II II HS AC TlvE II II I I II II II C H MUX ouT NCURSDR I I I I I I t I I _ _ I I L _ J L _ l 1 _L ___J 1 ___ LJ____ l l l_ L J L I _ FIGURE 8 0 VIDEO CHARACTER TIMlf...

Page 38: ...l J R29 i I I U IL__ __ _5_lb 22 U F 25 Vdr _ _ ________ 5 ill c C29 1 C30 J6 II C I C32 __ C35 C36 c lo CIIIt 2 z AI A NO SCALE NOTES 1 UNLESS OTHERWISE SPECIFIED ALL RESISTANCE IN OHMS ALL RESISTORS I SW 1 V W 5 ALL CAPACITANCE IN MICROFARADS ALL 1 S PART NUMBERS PREFiXED BY 1820 ALL TRANSISTORS HP PN 1854 0467 ALL DIODES HP PN 1901 0040 MASK BEFORE LOADING 3 MARK DATE CODE OPER 33 INSTALL IN PO...

Page 39: ... eER B480 0160 3335 C35 0160 3335 0 CAPACITOR FXD 470PF 10i 100VDC CER 2 B4BO 0160 3335 C36 0160 3335 0 CAPACITOR FXD 470PF 10X 100VDC CEI 2El4BO 0160 3335 C 37 o16C1 4tlOl 7 CAPACITOR FXD 100PF 5i 100VDC CER 2f l480 0160 4801 C3S 0160 3335 0 CAPACITOR FXD 470PF 10X 100VDC CER 28480 0160 3335 C42 0160 4554 7 52 CAPACITOR FXD 01UF 20X 50VDC CER 2B480 0160 4554 C43 0160 4554 7 CAPACITOR FXD OlI JF 2...

Page 40: ... ZNR 14 5V PD 5W TC 088 IR 5UA CONNECTOR 26 PIN M POST TYPE CONNECTOR 9 PIN M POST TYPE CONNECTOR 7 PIN M POST TYPE CONNECTOR lb PIN M POST TYPE CONNECTOR 34 PIN M POST TYPE TRANSISTOR NPN 1 TO 18 PD 360MW TRANSISTOR NPN N440 1 SI TO 92 PD 310MW TRANSISTDR NPN N4401 SI TO 92 PD 3 l0i 1W TRANSISTOR PNP II PI 310MW FT 250MHZ RESISTOR 10K 5 25W FC TC 400 700 RESISTOR lK 5 25W FC TC 400 600 RESISTDR 4...

Page 41: ...AN U47 11320 2024 3 Ie DRVR TTL I S LINE DRVR DCTl 01295 SN74lS244N U48 11 120 2298 3 1 Ic zaOA CPU 2841 10 1820 2298 U49 11320 1197 7 Ie GATE TTL l S NAND QUAD 2 INP 01295 SN74lS0 ON U i1 5081 2705 3 16K RAM 28480 5081 2705 U5 50Bl 2705 3 16K RAM 28480 5081 2705 l J i3 5081 2705 3 16K RAM 28480 5081 2705 U54 OBl 2705 3 16K RAM 28480 i081 2705 U i6 11 120 1438 1 IC MI IXR DATA SEl TTL lS 2 TD 1 LI...

Page 42: ...DIP SLDR 213480 1200 0607 XU44 1200 0607 0 SOCKET IC 16 CIINT DIP DIP SLDR 8480 1 00 0607 X1 l48 1 00 0654 7 2 SOCKET IC 40 CCINT DIP DIP SLDR 213480 1200 0654 XU51 1200 0b07 0 SOCKET IC 16 C lNT DIP DIP SLDR 28480 H OO 0607 X1 l52 1200 0b07 0 SOCKET IC 16 CUNT DIP DIP SLDR 213480 1200 0607 XU53 1200 0607 SOCKET IC 16 CIINT DIP DIP Sl DR 8480 1 OO 0607 XU54 1 00 0607 SOCKET IC 16 CUNT DIP DIP SlDR...

Page 43: ... FAIRCHILD SEMICONDUCTOR DIU SEMICON INC CORNING GLASS WKS COMPONENT DIV NATIONAL SEMICONDUCTOR CORP HEWLETT PACKARD CO CORPORATE HQ RCA CORP SOLID STATE DIV HARRIS SEMICON DIV HARRIS INTER TYPE SPRAGUE ELECTRIC CO COD E LIS T AS OF 12 01 81 PAGE ZIP ADDRESS CODE TOKYO JP MIl WAUKEE WI 53204 DALLAS TX 75 2 AUBURN NY 13201 PHOENIX AZ 85008 MOUNTAIN VIEW CA 94042 BURLINGTON MA 011303 RALEIGH Ne 2760...

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