Hitachi 505 User Manual Download

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Summary of Contents for 505

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Page 2: ...c Amplifier Balance d Changing Computational Components MONII ORTNG ANDCOIfIROL a Output Selector SL 25A b Overload Indicator OL 25I c Digital Voltmeter DV 25L d Multi Range Voltmeter in the Contror Panel e Reference Potentiometer in the Control Panel f Mode Control in ttre Control anel T nrnlrq 6 h Slave Switches i Readout Devices in the Control ane1 j Function Switches k ower Switches n tne Qont...

Page 3: ...e Generator FG 155A Functi on Generator FG 153A nerator FG 15I nerat or TG j 52 nerator FG L57 a a a a 8 OOMPAnATORS cP 151 CP I52 9 rlEE DToDESFD 151 10 TRANSIER DELAY ELE ENT TD 151 11 AIJIOMATICOTERATOR AO 151 T2 MODE CONTROL PANELMC f51 LL REFtrTIII IEOTERATION a02 a a a a t t t t t SECTTON IlI MA NTENANCE SB ARATED HIIACHT ANA OG COMPUTER TROGRAM MANUA L I Will EXPIA1NthE PTOgTAMM1Ng techniqu...

Page 4: ...ACHI 505 Control Area Readout Panel OC 151Patching Block and DVMT A4 to SEL Patching Qimnl ifiaä nhamxtis Of Reference Potentiometer Conneeting Ar a Rear the Comprting Console Potentiometer Patching Unit PT 151 and otentiometer Panel fr Z5t Potentiometer Schematic Showing ein 100 volts Potentioneter Loading 6O4 Pntantinmotp f i rr i e crm rified SchematiC v J L v Potenti ometer Schematic ea rdConp...

Page 5: ...h emrtic y f v f u r t r 4 u u r r 1 1 6 X2 FGrSimplified Schematic Block Diagran X2 FG Patchlng arrd Simplified Schernatic Log X FG Patching and Simplified Schematic Trigonometric FG Simplified Schematic and patching I J V U Ä U A J V A U sinX Patching and Simplified Schenatic cosX Patching and Simplified Schematic Pri nn i n l o nf IIF I VFG FG 151 Si nplified Block Diagram and atching H l n n r...

Page 6: ... 1 1an9fer Delay Element Typical patching and Simplified Schematic Äutomatic Operator Simplified Schematic and Block Layout Automatic Operator Block Diagrarn for Typical Connection and patching nlocklayout Mode Control panel patching Block Layout Timer Panel TM 25I Timer Operation Patching ...

Page 7: ...del has been constructed er eri rnents may 1 i _ 1 i be performed on this nodel in lieu of experi ments on the physical system Investigations which might be difficult to carry out on the actual system becone quite feasible with this technique For exa np1e a ptrysician may wi sh to study the effeet on blood presfllre in a cer tain portion of the brain in the event that a patient loses an ann It is ...

Page 8: ... board inserbed it is not necessary to use computer time otherSthan for actual comPutation T h e p r o b l e m i s n o w r e a d y f o r c o m p u t e r s o l u t i o n A f t e r m o r r n t i n g the proper patchboard the potentiorneters u otso are set to corre spond to the physical problem constants The computer solution is now obtained by pressing the rtcoMPUTElt button roblem variabfes may the...

Page 9: ... userr s particul ar problem c o r r n i n h a m r n r r r l i 1 a t l A h n l i n r i n n q l l o v n r i n q t h o e n a n i l D V U 4 P f l M l E l l l 4 l l U a J t U a U J s q ö P f r U 4 U r v l l D g y f r r p u r l u p y s v l a features of the Hitachi 505 for more adva ncedtechniques It incfudes function generation transfer fr mction simulation md partial dif ferential equation solution H...

Page 10: ...livered by a rnediutnsize laboratory oscilloscope The Hitac hL 5A5is nodular in concept with solid stat e components used throughout f The modular arrangement of the computer permits specialmachineconfigurationsdependingont heuserlsrequirements The componen arraJlgement allows sirnplified wiring color coding of the modules aids in rapid identification of elements and simplifies wiring checks The c...

Page 11: ...tion timer the digital logic rmit and the digital voltmeter The control panel located in the lower right hand si le of the control console contains the manual rnodecontrol s ritches a altmeter the reference potentiometer and Someexternal tnrü terminals Immediately above this rmit is a three channel oscilloscope with electronically generated scales The digital volt meter mormted above this oscillos...

Page 12: ...NOTES 1 Ti E DISPOSITIONCHANGED SLIGHTLYIN T IE LATERPRODUCTS 2 ONEMOFECOI PUTTNG CONSOIE JIAY M ADDED TO TIm RIGHT OF TI E ABO IECOMPUTER FrGUm 2 L L TYPTCAT 505 FRolflrvEW t T t t I A ...

Page 13: ... E l tj L r i n ft H fi F t HA F EQUTPPED FIGUNS 2 L 2 PFE PATCH ANELMODÜLAR LAYOTIT t FULLY EQUIPFED ...

Page 14: ... o r t i n g t h e p l u s r e f e r e n c e t o g r o u n d f o r e x a m p l e w i l n o t a d v e r s e l y effect the supplies output current drops to zero nor will the re ference supply fuse blow In addition the surface of re Patch Panel is covered with coloured plastic plates except frarne and handles re clucing shorting out of ha nging pat eh cords a reliminary Operating Considerations The ...

Page 15: ... t b srx coIrr EcTOR BOTTLE PLUG FTGURE 2 2 L AMPLIFIERI IITHSIX CONNtrCTOR BOTTLE IT UG PROV DT G FEqDBACK r r _r h rir l llr Ilr DA l51 9 ...

Page 16: ...DVMDV 251 ttRAtto votrtr swrrcH ADDED rN LATERttoDEL DVM ET 620 FTGURE 2 2 N DVM FROIfIVIEW ...

Page 17: ...ay be accomplished simply and rapidly 5 Check the plus and minus referenee DVMby selecting 100 red for plus and Paragraph 3 a 6 Allow about thirby minutes lrafln up time this assures that the computing components including the DVI and oscilloscope are up to normal operating temperature Ground the DW input ter nination designated on the oc 151 FEADOIIT AliET md confinn the reading is within 000 00 ...

Page 18: ...RESEabutton and then inrnediately depress the button for the desired mode This sequence of operation will prevent the possible momentary over load from effecting the problem solution b re atch Panel Insertion and Removal T o j n s e r t t h e r e P a t c h a n e l s e t t h e l i p o n t h e l o r r e r e d g e o f t h e panel in the quide groove f gure 2 2 3 Push the top of the panel in so the pa...

Page 19: ...t l t th FIGURE2 2 3 PFE PATCH PANELTNSERTTON _ L 3 ...

Page 20: ...t the arnplifiers of the 505 are balanced i e with a bias current is applied to the amplifier summing j nction equal and opposite to any current due to drift thus placing the surnnringjunction at virtual gror nd Once balanced drift in the amplifiers is el iminated automatically by the stabilizer circuit The d c emplifj ers of the 505 are ertremely stable and nornally do not require balancing for p...

Page 21: ...nd ing balance control The balance eontrol for arnplifiers A00 through A39 the operati onal araplifiers ar e located directly behind the re atch anel Figure Z Z 4 There are two balance controls in an ar rplifier They are voltage balance control and current balanee control In the BC mode when DIS button pushecl only the voltage balance is necessary Adjust these controls for a zero reading on the ne...

Page 22: ...L L t I VOLTAGE BAIAI C E CONTROL OF AIO VOLTAGE BALAI iCts CONTROL OF All CURTI IET BA ANC E CONTROL OF A _O CURHBNT BAIANCE CONTROL OF All FIGUFE2 2 t AMPLIFmR BATANCE CONTROL LOCATION r b ...

Page 23: ... H l z l a o A e t ä C E T J E H ä H 5 D d A G F r r o e h j e r t a i J J __ _ ln td t l o t H D u ö cf FIGUNE 2 2 5 COMPUTER COMPOIFfi T MODÜI E ASSIGNMBIfIAXSAS lf t ct rl c rt c cr t 9 i o a ä n a o _ rn l Z r _ __ H 6 4 B I 5 l ä r c cr l ca c 5 äG g l A o t H E _ a f ö H E C N P r r r Pr ir p i ä Pr F s n r a E 5 l q 4 l Z f l H _ tr 3 1 F _ m f aö v l 4z r t H 9 X o ä a ä o t ä _ F x x H l ...

Page 24: ...rangement of jumpers on the rear of the patching block f Computing Module Replacement Removethe re atch Panel to expose the conponent modules Removethe two phillips head retaining screlsrs from the top and bottom of the module to be removed figure 2 2 6 b fnsert the special nodule removal handle in the hol es pro vided next to screi rholes from which the screws were removed Attach the two screw kn...

Page 25: ...FIGUFN 2 2 6 RM IOVAIOF COMzuI NGMODUI E r I 1 T h r l r l n l l r l i l n n rl t q ...

Page 26: ...FIGURE2 2 7 ATCHING BLOCKNE T ACM4ENT ...

Page 27: ...tching 3 MONITORING ANDCO XIROL The control system of the HII AOHI 5O5is designed to al1ow simple control and monitori ng of the conputer components Figure 2 3 I The following sub paragraph descri bes the fr rnction and operati on of the various monitoring and control facilities of the 406 a Output Selector SL 25I T h e o u t p u t s e l e c t o r n a i n l y c o n s i s t s o f t w o r o w s o f ...

Page 28: ...TOR 1ITCH TRANSFER S1 IITCH CONTROL ANET N COM IIII GCONSOIE OUIPUTSEI ECTOR FUNCTIONS1 IITCHES AUDIBI EALAR4CONTROL SI IITCH UVEFJ OAD NDICATOR i VOLTIETEN RANCE S IITCHES I I I I TIfiSE TRUNK LINES TERMINATE ON FEADOTN PANELOC 151 FTGURE 2 3 T H TACHI 505 CONTROL ANEA ...

Page 29: ...ugh A19 are set up for sel ection The button in the second row designates which of these ten amplifi ers is actually selected The selector system button numbering corresponds with the amplifier and comparator designations as marked on the pre atch anel respectively The selector system output is connected to the ten terrninations marked SBL in the upper portion of the Readout ane1 0C_151 tr igure 1...

Page 30: ...plugs rolonged overload will not damage an arnPlifier T o e l j m i n a t e t h e a u d i b l e s i g n a l i n t h e i n i t i a l o v e r l o a d i t i s recorunendedto turn off the s r litch designated AIAIM on the panel c Digital Voltrnet er D i 25I ThedigitaJ voltrneter wu Dv zsListerminatedintheReadout anel 0c 151 area Figure 23 2 and is designated DV As previously mentionedtheDVrraybebottle...

Page 31: ... r5r o fl r SYNC o RR o FIGUm 2 3 2 MADOUTPANEL0C 151 PATCHI GBI OCKAND DVTiI VMTO SEL PATCHII G r t t T t l f f 1 l r r MADOI T PA EL o l r l in n 2 nA H t l sn c o o o o lo CONTROL TRUNKS O OrO O rQaQzQ o oc r5r o _ 2 5_ ...

Page 32: ...tch Panel driving switch the RANGE switch is connected to the re atch Panel Vlil terminati on Figure 2 3 2 pennitting this point to be bottle plugged to the SSL output or as in the case of the digital voltmeter monltoring voltages at nost Pre Patch Panel t eruinations via a patch cord Following is a list of the voltmeter coru ections in eaeh mode of operation with a brief descripti on r r r r t r ...

Page 33: ...ul1 meter men t i n n a Ä r l n o q Ä r r e 4 r v e q J In the state that the NULL button is not depressed the re ference potentiometer may be used as an ordinary potentiometer tesninated on the FUNCTION SWarea of the Pre Patch Panel f gure 4 t J In the state that the NIILL button is pushed dor rtt the re ference potentiorneter may be used as arms of the null meter In this state the reference volt...

Page 34: ...d t r r r r t t t I I oRDTNARY PorElxrroMETER coNlqgcrloN TIE STATENI LL BIJTTON UP 1001 o NULIUETER sTsTEl coNNECTToN TI E srATE NUII BUTToU ocmlN FTGUFE 2 3 3 SIIßT TFMDSCTIEMATTC OF IEFEMNCE POTENTIOIdETSR 2 8 ...

Page 35: ... depressed all integrators are sj ultaneously released to respond to input signal voltages The integrator outputs change in potential as dictated by the inputs a time varying behavior is produced This generates the voltage solution of the progranmed probleni Depressing the HOLDpushbut ton pennits the problerL solution to be halted and all voltages held at the potential attained up to the instant o...

Page 36: ...ecial i y in separate mode con trol operation The FE 0P button s witches the conputer into the re petitive operation rnode if the oscilloscope 05 251 or the tiner TM 251 or IM 253 is provicled in the 505 In this node the each of the integrator capacitor will_ change to the capacitor connected to the terninal cle signated R0 on the integrator area of the pre atch Pane1 if the IIITEGRATOR CAPACIIORs...

Page 37: ...the right rear of the computer figure 2 3 r These connectors may be used as outputs to accessory equipnent or the tnmk terminations may be cabled to a second eonputing console CS 505A as signal carrying lines for the interconnec tion of the problens patched on separate re Patch Panels of slaved computing consoles Control trunks terminating at the Readout Panel 0C 151 ar ea provi_de point t o point...

Page 38: ...d The slaved conputer then responds to the selected modes of the master computer pushbuttons I trhena 505 is to be controlled by the Digital Elenent Panel or the Timer the button INT of the SLAIIEarea is de pressed Then the conputer is driven with sigrals from input of the analog patchboard or the digital patchboard For normal ma nual operation the OFF button of the SLAVEarea should be kept dorm r...

Page 39: ...Ä z F H E l co R o rn I a F l o a 2 o J Ff o d 94 z h o l l z ü H r E o F f H o E f E A o o o f H d dä E p E H E b t r z t d D H r 4 HHEH E S A E Oi FE trl O I E i H J s d E E ä Pr ü L H frH F1 Z F I H H z a t o H f H F F F J Q H frl tn O E J H o o G l P r c D H z a z o O ztÄ H d Fq l lf I r t O a z J ü z H ts D E o 14 ä E FIGUnE 2 3 CONNECTING AREA F EAR TIIE COMPIIIING CoNSOT E CS 505A t 2 ...

Page 40: ... when the computer is placed in the high speed nEP oP mode of operation The recorder terminations oR the Readout Panel are wired to con reetor plugs at the rear of the 5O5 See Figure 2J4 Oscil loscope OS 251 is especially prepared for the exhibition of the eomnrrtez snlrrtion The OS 251 has three ehannel inputs and can be mormted on the control console cS 505B Al1 input terrninals are con nected o...

Page 41: ... computer is the multiplication of a variable voltage by a ignal The Hitachi 505 has a basic complement18 potentiometers and may be expanded to a full complement of 54 potentiometers Each Potentiometer Panel H Z5t provides 18 potentiometers for ser ting problem coefficients initial conditions and problem inputs The potentiometers are mounted to a maxjmumof 3 horj_zontal rows of 1g poten_ tiometers...

Page 42: ...i o m e t e r i s l o a d e d a s i s t h e c a s e w h e n i t is used as a computer problem element Norma11y the pot is loaded by either a lM or locK ohn resistor since a potentioneter generally feeds anamplifierandthesevaluesarethemostcommonanplifierinputre s i s t o r s F i g u r e 2 3 i l l u s t r a t e s t h e e f f e c t o n t h e e j f e o a n d R 1 l R 1 ratios r rhenthe potentiometer wi...

Page 43: ...PATCHING UMT FUSELOCATION FBARoF Porm Tro ßTER PANET POTENTIOIMTER ANEL FIGURE2 r t P0Tm TI01 1ETER ATCHING UNIT FT 51 AND OTE1 IIIO ETER ANEL fr Z5T 3 7 ...

Page 44: ... i1n is 3 33 ma iL O eo 100 3 33 5 83 3VgLTS F r t 0 833 AS SETBY DIAI rt o _ 93 3_ n e ö i v v r_r1 l 00 R 1 n R1 ei n FIGURS2 U 3 POIE1VIIO ßTEN LOADING T lD rtl I Lo elrr 100V e o väJJ CONS DtrNED tltnrnir np o t o o R l l o n K o Rt iirt I i ia RI t l I l L0 4 D 100K t t t t t t t t t T t I I I I I I I I t rnnr v LOAD DIAL SETAT 0 833 RL 25K R2 5K eo 100 i1r R2 ii1 1 i1 i I IITH100K LOADiir r ...

Page 45: ...absence of the DVM a nul1 pot cir cuit The operator may then set the wiper for the attenuation factor required in the problem The method of the setting the ungrounded potentiometers is quite sirnilar to the setting the groirnded ones The 1ow ends are transfered from the Pre Patch Panel terminals to ground in the pot set mode Figur e 2 1 5 shows schematics and syrnbols for the two types of potentio...

Page 46: ...A iEL Lo TERIITNATION FIGUF 2 L TO IfiER TFE ATCH ATiEI TtrJO4INATION TO NEADOÜI SEIECTORSYSTEN A GROUNDED OIE fIIOMETEA CIRCUII E ri I t T I I I I I TO l lIIER FE ATCH ANELTEF 4INATION F TO 0T SE ECT R SYSTM4 b UNGROUNDED POTE Tff O 4EIER CIRCUII 505 OTE1 Tr0 IBIE R ClRCUrrs S MPLTFIEDsHm4ATrc F ...

Page 47: ...T SCHfl ATIC b GROUNDED 0T CO 4PUTEfi DIAGRAI I S ßOL t x y y rx r K y t fx v v KX 1 K Y c UNGROUNDED POT SCIß IVIAT C FIGiIFB 2 4 5 POTENTIO ETER SCHE I ATIC ANDCOI PUTER Sl vßOLS d UNGROUNDED POT CO PUTER D AGFXMSY ßOL NOTE K eo ei ...

Page 48: ...bracting square root generating 1 a i h m i a f r r n n i i n n a t a v 5 4 f u r l r r To understand the basic concept of the operational amplifier consider the simplified block diagram of Figgre 2 5 L where a high gain arnplifier gain of A has a feedback i rnpedanceZg Egß an input impedance Zin The amplifier is designed so that it has three basie and essential characteristics 1 The amplifier out...

Page 49: ...FIGUNE 2 5 I O ERAT ON LT A 4PLIFßR S MFT F EDBLOCKDIAGRA I n h l I l Ft h llr llr Ft f I FI E FI F 4 3 ...

Page 50: ...important considera tions of the operational amplifier The inpgl_g1lput rela i9ne4 1 f Orl LY the operational arnplifier is so1e1y de t on the ratio of the feedback to the input imPedance using Equation 2 5 3 as the basis of discussion the following subparagraphs describe the various uses of the operational amplifier r l h r t A h d a h ir lhenthe same value resi stor is used for both the feedback...

Page 51: ...tion by a constant ldith R1 equal to l I4 and R3 equal to 100K for example the arnplifier output is M oo IOCK oin lu ein An input of plus 10 volts results ln an output of minus a hundred volts This operational amplifier has a gain of ten The multiprying constant can be made less than one by using a 1OCKfeedback resistor with a LM input resistor e looK ein 0 1 elrt l M An input of minus 100 volts p...

Page 52: ...suming an initial charge on the feedback capacitor of Vo Looking at this another way if Zf is a capacitor having an operational impedance t fi and Zi 1 is a resistor the basic opera tional arnplifier relationshipr Equatlon 2 5 3 becomes F in L au 9 Jrr o R C R C l o With this arrangement the operational amplifier will integrate with respect to tjme any input voltage In addition to integrating the ...

Page 53: ...non linear characteristic can be approximated The arnplifi er can also be used in conjr nction with diodes and z esis tors to sjmulate the non linear operations of ljmiting dead zone generation X2 Logf etc b 505 Operati onal Anplifier DA 151 Figure 2 5 2 shows the operational annplifier patching terminations and a simplified schenatic of high gain d c amplifier and summjng re si stor network By pl...

Page 54: ...DUA L DC AMPLIFMR O O A SIMFT IF EDSCI EMATIC OF 1 THE DUALDC A IPLIF ER CURRE EBALANCE CO TIROL VOLTACIE BALANCECONTROT oItrRATIONALA 4PT IFIER STMPLIFmD SCHEMATTC AND PATCHING BLOCKLAYOUT UA J ...

Page 55: ...1o Xt X2 x3 Xtn FIGUnE 2 5 3 SUMMER AI 4IT IFIERPAICHING eo X1 X2 10X3 r101f4 N0IE IF A PLIFIER IS N0 USBD BO TIE PIUG REQUIRED TO RWIDE IEEDBACK b r t t h T l l l l r 1 l 1 f l r t t l r t f l f l 1 DA 151 9 ...

Page 56: ...antl reset buses Normaly these terminations are corurected aS shor rnj n Figu e 2 5 l hor rever by cross patching nofa bus to reset relay etc the integrator can be used as a track and hold unit An additional feature is the free tertnination of four integrat ing capacitorsi 1d 1 dr o1 uJl and oo1 uF They ar e correspond ing to the integrating gains of 1 10 1OOand 1000 the operator has the choice of...

Page 57: ...10 1 t l I t t t l t l t t t I t 1 l T _ 1 o rd J x1 x2 x3 r1ox4 10x5 ot rc a T TEGFATOR PATCHING X Y X3 Xt c COL PUIER DIAGRAtitS BOLS NüIE F AMFT IFIER IS NOTUSED BOTTLEPT UG REQUINED TO IB OVTDE IEEDBACK PATCHINGAND D AGRAM 5 r 100K M tM lM FIGünE 2 5 INTEGRATOR ...

Page 58: ...E TXIIECIR TOR CAPACIIOR BUS POT ST BUS AIL NESET BUS 1 ONLYONE0F Ti 10 IIWEGRATORS SIiOl lN 2 T IES FOIIRCON EC TIONS NORMALLY MADE BY BOTTI E LUGS 3 RELAYSSHOI IN DE ENERG MD t t T t t t T t t I I I f FEr tl t I FIGUFE 2 5 5 INM GRATOR AMIT IFER ANDS MFT IF 3DSCHEMATTC aa 4 _ 1 _ ...

Page 59: ...tsGRATING GAIN RT 1 R0 100 INItsCTRATING GAIN RT 10 R0 1000 t rr 1 0 nh no z W ffir r t l 1 n Z b ö t o b J C MM c ru 2 X WW I Iv I r ä A J INTEGRAT NG GAIN 2 0nDTNARY OrEnATroN 2 I ruEGRATTNG GAIN RT 1 R0 1000 F r l t I t l l t l t l f t T T l t 1 I 1 t_ RT L0 R0 100 5 3 ...

Page 60: ...N 151 3 SmcrAL OTERATTON 1 MODECONTROL BY MODEMATRIX IN D GIIAL LOGTCAREA TIE IIEGRATOR CO IPI IESIN HOT D MODE Tr SMCIAL OTERATION 2 TIIE INTEGRATOR COM UIETS N NESETMODE TI EINTECTRATOR IS COIüTROLIED BY TIiE TIMER TO T MER OUIPUTS 5 1 ...

Page 61: ...151 F t r t t l t l I t l l t 1 1 t I t t TI E ATCHINGSHC I S TWOORDINARY INIEGRATORS HAVINGTtfr CIICUITS BELCIvI 1 1 I 10 10 N FEP OPMODEI IIEC RATINGGAIN E MIJLTTPLIED BY 1OO t J 1 1 10 10 DUAI DCA IPLIFIER o o n i l tuJ I clt QV TN o FT_151 IT2 l o DA 151 o o rN 151 5 5 ...

Page 62: ...ing cireuits of the multiplier Each diode is reverse biased cut off by the negative reference source at a potential dependent on the series resistance n4t ntrZ R6O in the reference source 1eg To eauso a given diode to conduct the sum of the X and Y input applied via the zumrning ampli fier must attain a potential opposite in polarity and larger than the bias of the reference 1eg By neans of apptop...

Page 63: ...4_ xy 100 YrV SQUAR NG CIRCUTT FIGTJnE 2 6 L MULTIPLmR SI PT IFIED BI OCK DIAGRAM 2OOK SQUAS NG rfr r o r 10 nA 4 U 100v n l l t r Y i 4 f 5 7 ...

Page 64: ...and X Y 1 should be squared individually Figure 2 6 3 is a simplified schematic of the quarter square multiplier showing the patching tenninatj ons and the patching btock area of the Pre Patch Pane1 For rnultiplicati on division or squaring a bottle plug is placed as shomr in tr ig re 2 6 and 2 6 5 respecti ve1y Note in each case the syrnbols of t he area the plug to placed indicates the function ...

Page 65: ... I OK IN MJLTIPi IER FIGUNE2 6 2 SQUARI IG CIR UIT SIMPLIFIED SC IEMATIC ö U O U tO 20 5 9 ...

Page 66: ...t t t I T I T I I I oK NOTE AMPIII IER SARENOTINTILUDED IN pI JLTIFLmRNET ORK Et 151 FIGJRE 2 6 3 VIULTIFT MR SD PL FIED BLOCKDIAGRSM AND PATCHING BLOCKLA YOTJT IviiJLTIPLIgR o o o o a _nl r _ a __ _ l __ n pa YbY cKo ...

Page 67: ... DITIIER SMOOTHII IG Y XY BE CO II I TED TOG T NF T d n 1 n l _LD LU1 it J1I a l l l l t t t _ l l l I t _t _t PATC INGA D SIi FT IFIED SilnilulÄTlC A 1 L MIJLTIPIIER obl o 3 ga o EM 151 NITI fO E K XY F GUAE2 6_ U M LT FT ICATTON ...

Page 68: ...e positive in polarity The following restrictions must be observed when using the rnultiplier for division i 1 The absolute val ue of the divisor X nust aluays be greater than or equal to the absolute value of the dividend Y i e lvl lxl r I r l l r l l 2 The divisor X must be positive 3 The divisor X nust never equal zero The quarter square nultiplier may af so be used to generate vari ous other f...

Page 69: ...X Y x 0 X MUSTBE POSIT VE NOIES FIGUNE2 6 5 DTV SIONPATCII NG AND S MPLIFMD SCHEI4ATIC l 2 i l l I I I I 1 1 I 1 a i a l l t 1 l t I I MULTIPLIER o EM 151 ...

Page 70: ...ted instead of a diode md supplies a suturation cutsre instead of a single brealc point ft gives an a operator a sirnple way to set up a firnction a X2 pixed Function Generator FG 154 A The 505 X2 fC accept both positive and negative input voltages and generates either a X2 or a X2 output Figure 2 7 7 is a simpli fied schematic of the X2 generator circuit showing the righ gain arnplifiers as norma...

Page 71: ... rli i iT l I I I I 1 I 1 I I 1 I 1 I h I I I L r li l J 100 d ri I irrlfJ ri i ai sr lr i r qr s a f l L t i T R r r r _ ü t I i j l r MrNJS crRCUrr I _ _ _ _ J Frcunl 2 7 L x2 rc srMFT rFiED scHEt ATrc o ...

Page 72: ...l J I oö F C C tl o l N o I o _3 ur o o c9o c c p p ö ö sq n r J i oo b 9c rt1 tN a F _ J n r dddo o FG L5L TERT IINA I TI J SHOULD BE CONNECTED TOCETIIER IF DITIER S 4OOTHING IS NECESSARY FIGURE2 7 2 X4 FG SIMTT FMDS CEMAT C ANDPATCIüNG BLOCK ...

Page 73: ...endix J c Trigonometric tr rnction Generator FG 153A Tho 606 Tz ionngnslric FG eontains two individual Trisonometrie f rrns L L L g v t f f E v r r v l r v tion generators both of which are terrninated at the re patch panel Each generator accepts a voltage of eather polarity Figure 2 7 illustrates simplified schematic and patching block layout patch ing to generate sin X ald cos X are given in Fig...

Page 74: ...J L t 5c LOG rorx1 xtttt 101x e 50 LOG ror 50 LoG roLr R2 I00K 50LOG ror 4 NOTE Rl ANDR2 OHMS IN AIL CASES C JTzuTSARELOGTO BASE10 PÄTIHINGAND S MPT IF EDSC 181 AT IC 6 t 3 rY IN o x ro 1 2 R1 100K F GURE2 7 3 LOGX FG ...

Page 75: ...D SCIffiMATICCOHRESPONDS HALFOF THE PATCI ING FG 153 il I 1 1 r I I l 1 l I l 1 1 1 I l i 1 I FIGUNEZ I TRIGONOMETRIC trG PATCi ING BLOCK SIMPLIFIED SCHE 4ATIC AIVD LAYOUT sinX trG o tä Fts coloc Q alQa co a p o Fc r53 o Y ...

Page 76: ...t r r t t L r r r t t t t I t t t I I o o l a n q J F _ P L 200K 2OJy 5OK sinx FG o t rs FIG TRE2 7 5 sinX PATCHING ANDSI4FT IFED SCI trMATTC ...

Page 77: ...F 7 t x r c FIGUFE2 7 6 cosx PATCIIING ANDSIMIT IFIED SCHEMATIC 7 r ...

Page 78: ...inpllfied Schenatics Figure 2 7 8 shows the VFG patching area and the slnplified schernatic of the overall unit the plus and minus VFG portions show only a single transistor gated re sistor circuit for clarity Figure 2 7 9 shows the patehing for using the plus and minus VFGIs separately this figure also contains a simplified schematic of the plus VFG The mimrs VFG is similar except that the bias v...

Page 79: ...he operator to set the change of the height to each preceding segnent by a voltage of zero to tl OO volts Figure 2 7 12 is a sample output curve of a VFG This cunre is used as the basis for the typical VFG set up pro n a Ä r r r a The foll_owing procedure is for the set up of a vtrG patched as shown on Figure 2 7 12 The set up adjustments of the VFG nust be started at X and contj nued in sequence ...

Page 80: ... n l I I I Eil Eo2 s o z l V t i t t l I l E i 2 F GUFE 2 7 7 FR INCTPTE OF VFG I H 1 I I Eon I ...

Page 81: ... ftt 5 H 4 o J co F trl H h H lf Pr E H fA j r rJ I FE tr oo I t c l l 1 i P 5 H h B O z H R r Y l r I cr I H I P r Z I H l E L _ _ _ i F l r 1 I h I 1 I I I t 5 f l t l I H I H r H o l I L____ H Pr h a o O O ri I z H t l a o ...

Page 82: ...I z H F4 H J f4 rI H pq tr 6 r l LN rl I ü h h o I f c r C5 H Fq l I I I I n l F r F J I P l a t I F t I J 6 l 1 _ l I I I I I I a l I E 4 l H I h l Br C I o l r i t B O rl J l l r I l r l l l l r h FT o o g al J ö ö r V rF j l X U l a ...

Page 83: ...l q or t r i j r O O rt J trr l I F r I l r n p l k l I H L_ F r l i t r l H L r O 6 O rt I z t 4 a F _ t l ä t l E I J J 11 A t XHd Xr t E Y t o ö l It ö l L J rnEnr I V V I ESs sl t l l t L l l r l t t l ü Ftr a is öLS H F z H 7 7 ...

Page 84: ...AND ASSOCIATED PRET ATCH PANELAXEAS FIGTm il 2 7 LL VFGCA RIL0CATION SH0 IING CHASSISIN SEt UP POSilION FGO3 FG0 1 FG0 2 FGl t FG1 2 FG2 1 FcZ 2 O IER LOAD AMPT 0I o5t TW o5r DITH ER FG o57 FG o5u OR FG o52 FG o51B utt FG o52 FG 051A OR FG o52 FG o51e OR FG FG 0511 OR FG FG n41 R OR FG o52 l Ö ...

Page 85: ...ing the output to the value o f F 0 Turn the SET RESET switch of F1 to rfsETrrside and adjust the F1 potentiometer by rnatchi rg the output to the value o f F 1 f Proceed in sequence number of F for the table For optimum accuracy repeat the set_up proeedure start_ ing with step c Turn the rrSET OIE rswitch on the card to rfOIEil side e Variable Fr nction Generator FG_152 The vFG FG i 52 is the sam...

Page 86: ...Y rr volts 100 80 60 A 20 20 40 6D 80 100 X y f x U O 10 0 t i 1 0 30 70 40 90 50 100 60 90 7O ou 80 20 90 10 100 öU SAIvI IEIJFG OINPM CüRIIE 8 0 FrGUng2 7 12 ...

Page 87: ...tc change a porbion of the set up fr rnction The principle of the FG 157 is explained on Figure 2 7 13 Figure 2 7 14 illustrates the patching for ordinary use of the Firnction generator The following procedure is for the set up of a FG L57 for posi tive input patched as shoi rnon Figure 2 7 12 The set up adjustments of the FG a57 must be star ed at FO and continued in sequence to F10 on the functi...

Page 88: ...T I I Ij1 r t r t t r t t r t d r t t r r L _ _ _ _ _ J STMPLTFTED BLocK DTAGRAM F Ei I b TNPiJT ourPUT nsLATroN FIGUNE 2 7 T3 PN INCIPIE OFVFGFG L57 E i ...

Page 89: ... F1 switch to trFrlsETrrside after the adjustments nentioned above f Proceed in sequence the above adjustrnent to the greater m iaber of F for the proper voltmeter and DVMreaclings as listed ln the table Note that the value of Xn should not exceed the vah e of X6 1 in the above settings g Turn n0 E SETtt switch on the cord to tfOlErr sicle If the both polarity of input is necessary set up the flmc...

Page 90: ... r t t t t t t M o Ff ü z H r H P p z E 5 H o 4 J o Ff m A E H Fq H a l H ä H a cr rl I tr C t E H Fq O Fr pl t F l F H 7 E U 1 O i l t s v Eq Ll I t u 7 H 2 lrI tt o O Q d o l r1 5 F l b O n N ItrJ LC lr l t lr 1 l l 1 5 o ...

Page 91: ...rator patching area and a si nplifiecl schematic of one of the comparators The other conr parators are identical The relay termination indicated by the negative sign is the position of the relay when the sun of the INl and IN2 input is negati ve this is the de energizecl position of the reLay When the srm of the IN1 ancl IN2 is positive the relay energizee ancl tbe raiper swings to the positive co...

Page 92: ... h fl r NET AYGROUND COMPAR ATOR AMPIIFffiR NOTE COMPARATOR RELAYSHO JN DE ENERGI D AREAAT DSIMPTIFMD SCI EMATIO ö o nD t a l FIGUNE2 8 L CO IPARATOR PATCHING ...

Page 93: ... an input to the rNl tennination equal in rnagnitude and potarity to the desired switching level b corurect the wiper of a potentiometer to the rN2 termina tion apply reference opposite in polarity to the IN1 input to the potentiometer high end c Adjust the input to rN2 so the comparator relay is aetuated as required when rNl r eaches the siaitching Level rue ootput of each comparator c ur be sele...

Page 94: ...FREEDIODES ffi 1 ffi 1 ffi 1 ffi 1 ffi o FD r51 o OrrO O O OilO OrO o o o o Cre c o ONO O1 O M M H O_ O M M ffi M M M i FIGUIE 2 9 L FREED ODESPATCHING BLOCKANDSCHBMATIC d A ö ö t t t t t T 1 1 ...

Page 95: ...ximation can be approximately produced I this connection the delay tirne will develop to the sr rnof the value set i n two elements Set a half or nearly a half of delay tfune on each element For better simulation the fourüh order approxfina tion rrril1 be recomnended The Transfer Delay Elenent TD 151 has a wide range of delay time br rt combination of both R ald C which make the delay tiroe T rnrr...

Page 96: ...oN rN cAs DELAYtrI4E IT SHOUTD BE NOTEDTHAT OUTPiNSIGNAI POI ARITYIs JUST OPPOSITETO INPI T IN A SIGNIE TD 151 O ERATION TABIE 2 10 1 DELAY TIMESETTING TASIE t T T T t I I I I I I I I I INPIJT Mfi IMIM ANGUI AR FNEQUENCY W MÄXN UM DELAYT I E M NT4UM DELAYTI ß CAPACITANCE TO BE USD BET IEElI 0 1 1 0 11 SEC 1 CAln 1 I ß D 1 0 1 0 1 1 0 0 1 0 1 10 l 00 0 11 0 00r 0 01 100 1000 0 011 0 0001 0 00 9 0 ...

Page 97: ...tchcords An illustration is shovm in Figure 2 LO 2 Ascertain t he function applying the jnput and watching the input and output on the oseilloseope if possible This will reduce the difficulty in the analysis due to errors in patching or inadequate RC selection In the patching of the capaci tor the circled terminal in RI or RO area in the Pre atch Panel Should be connected tu the circl ed te minal ...

Page 98: ... t l L g NELAY GROUND NIEGRATOR CAPACITOR BUS TRANSFER DELAYEiiEMEIru SIIvIPLIFIED SCHB ATIC AND PATC IT JG BLOCKLAYOM TRANSFER DELAY n O o 9f H l 1 t 1 Ielg Hfi o t n E F 0 t FA o ö l yr_ r ll r n 7 va il IN R or r v v _ o ö A v TD l51 o 9 2 FIGURE2 10 1 ...

Page 99: ...NELAYTI 8 0 1 SEC SETT NG FORNT OTERATION t t t t 1 l t l l l l l t t l l l 7 I 2 0 2 TRANSFER DELAYEI EIVENT TYPICA PATOH NG ANDS MFT IFMDSCI EMATIC trl p t E E 40K o TD 151 9 3 ...

Page 100: ...integrator in the A0 l 51r refer to the one of the Integrator IN f5f L2 MODE CONTROT PANEL MC 151 ordinally the computer mode is controlled by the mode control switch on the Control Panel and occasionally the operator will feel tho noness itw to nnntrol tho comnuter automatically through the patch u l l v l l v u s o D r u J v v v v r r v r v ing on the Pre Patch Pa nel for instance from the compa...

Page 101: ...4 A O J F H O F F f Z f l H t r i ü o z E H H Z H O E H l 1 j ü F i t r O a b 2 ü F l Fq t H I k l n fr rl 8 r l H Ö O H Z Ftl p E s H H e c o H a g ö a HHH E fH HHA HH EEE E t r E E E t r o ts o ö n Fr l J A r i____J 9lq o U ä r l I q r u l r rE J E rJ FA a f l r l d l d c rrII 3 f l l t f r lsl J r r O Eo J q l q r tqlr l t l 9 5 ...

Page 102: ...ig E H ä H 3 ä 6 H ö ä U H F I F i i n l o z t Ä 9 3 r q F E F 9 H A v E r ü e u ä g r l H r q L r i H S H o r ä E N E C J b H J A E H O J r H ü E r l H 9 IE H 8 v H 5 5 i b z A Y t H c r l F ä H r H C i I I t r n V c a F r H f 4 C H E H O E Ä _ o H d tlr o 9 6 ...

Page 103: ...r FIGÜNE 2 I2 I MODECOMROLPANELPATCITING BLOCKLAYOlff f T F F r h h r I 5 5 I 5 5 5 5 5 I MODECONTROL o o o o ö TIYMRS OOO O y 0A 9str oo x ooGo o MC r51 9 7 ...

Page 104: ...plies three timers which can be operated i n d e p e n d e n t l y o r i n a s e r i e s c o m b i n a t i o n 0 n t h e T i m e r a n e 1 t h r e e timers occupy the center space with three pai rs of the time setting d i a l s a n d a b o v e t h e m t h e r e a r e t h r e e p a i r s o f j r r d i c a t o r n e o n l a m p which wil_l inform time sequence of the each tj ner operation These time...

Page 105: ...FX 2 I3 I TIMER ANEI TM 257 11 f l t r 1 T i r t I l I I t t l t l l l I 6 TIMER PANELTM 25L v K I v 0 o TT4E SETTEf c AR E FTNT TIIIE SEc 5 MULTIPLIER o ol o l o oo z Tt 4E tEc oöt o t E S AAELE COMDI 9 9 ...

Page 106: ... i v e o r i t e r a t i v e operation can loe accomplished by adjusting the Ti mer 3 setting to zero I n t h e s e r i a o p e r a t i o n t h e R U N s i p a l o n t h e P r e P a t c h P a n e l s h o u l d b e applied on the IN terrninal of the Tjmer 0 The Tjmer Panel is controlled with two other signals ST0 and CLEAR The STOPsigral holds the Tjrne operation momentary in series conbi nation st...

Page 107: ...i TO fMO IN T IIS GROUP OIERATION IISTOP ISIGNAI IN A TIMER OIERATION OST ONES TIü I Z T MER OTERATTON TO TIIE T TIME TMOrtONrrSIGNAI iILL BE AP T ED CONTINUOUS ÜSTOPII A dDTMO ON I S GNALSWITHIN AN OTERATION TnlA 0F A TII ER IIILL N0 AFI1ECT TI B TX4ER O ERATES TMN AS TF NO S GNAI TS ADDED I srr rn n l l ir r l I TI to I cFr I nlro RUN l sErrxE l T1 10 OFF coue rlt o rroN orERATroN TMO 11 11 Tlil...

Page 108: ...ected to RO terrninal TL NEIETIIIVE OMRATION The addition of the high speed repetitive operation feature to the 505 provides means of rapidly switching the computer integrators b e t w e e n t h e F E S E T a n d C O M P U T E m o d e s a t c o n t r o l a b l e r a t e s u p t o 5 0 c y c l e s p e r s e e o n d c o n p u t e t i m e l O m i l l i s e c o n d s r n i n i r n r r n T h e c o m put...

Page 109: ...between the integrator reset anc the compute modes means that a problem is solved reset and then solved again this pro cess continues repetitively at the pre set rate The problem solu tion may be displayed on an oscilloscope that is s mchronized r rith the Rep op cycling rate The inputs to the oscilloscope are ter ninated on the Readout Panel 0C 151 To place the computer in the Rep op node the ope...

Page 110: ... l SU IVIING A 4PT IFER SoLrD_grATE DIoDE I üTEGRAT ING A 4PL IFIER _ AAA FI GD NESISIOR AIND SETPOtENTIOMETER rr CAPACIIOR I GROUNDED 1 _ I rr l r t a ryry_ sET_ PorEltrro _ V METER UNGROUNDED I l o Y INPUTOFXY X INPUTOFXY PT OTTER PLOTTER _lVlr xY _1AV 1oo QÜA3fER SQUAFE MULTlFT CATION MULTI I IEX MODE I T T o I l r T o FSLAY COMPARATOR IN I N 2 l i _ I v e ...

Page 111: ...O TETER l l I k p TErrrr ror ßTER SETTTNG 2 UNGROUNDED POTENT OMETER k e1 e2 u1 Jtt r u r 2 I T o 3 TNVEnTER lT MULTIPT ICATION BY 10 10e 5 MULT PI ICATION BY K for 1 k 10 for k 1 use circuit l f a a Ä i n c n i 2 r e v q r r r S v L L v q L v J ke k 10 10 6 MULTIPLICA TION BY 2e 2e 7 I I LTIFT ICATION Y e1 e 2 l_ e 2 LU ...

Page 112: ...T DESCR IION 8 MULrrPLll f to tt K l i rL J l u _ L _v q MULTIPLICAT ON BY AN ARBITruSY VALIJE K e1 t0 2 1 K K e1 10s2 10 ADDITION r ez el 11 SUBTRACTION Vo l 1j N zrllV 21 V eo J et 1oe 12 IIV1SGRATION bt r t t t t t I I I I ...

Page 113: ...j l I t I t t l l J l l I t l J 11 _i l _i 1 i _ 1 r I MiJLT IPL CATIOTI XY tbo COMPUTER DIAGRAM X Y S MPLIF ED DIAGRA XY PATCHING DIAGRAM r T d T A a r 1 UIV LDIUI X Y 100Y Ä PATCHING DIAGRAM S MFT F EDDIAGRAM COMPUTER DIAGR AM 100Y x ...

Page 114: ...IXD DIAGRAM x 0 I N l X Y ry K A 1 S l v R r I 1 n r 1 l YI t I n F Z1 t t I F FV 2 o f a _ oo oo G7 r w J vwL PATCH NG D AGRAM COMPIJTER DTAGRAM l X MIT IFIED DIAGfuT I x 0 IF TIIENE IS ANY OPPORTUIIITY OF X 0 DIODETEEDBACK SHOIILD BE APPLMD r _ N x F ö F NOTE f00 ...

Page 115: ... x F rr r o 11 Ii F o I o o ono oto 9 T0ö __x2 100 COMPUTER DIAGR AM PATCH NG X X2 100 SI4FXIF ND DIAGzuM x 0 DIAGRA 4 Jloö m X COMPUTER DIAGRAM J ioo Kl X PATCH NG DIAGRJM S MFT IF ED D AGRAM x 0 NOIE IF THENEIS X 0 D ODE APPLIED ANY O PORTÜJITY FEEDBACK SHOULD OF BE t n q ...

Page 116: ...APPEND X4 4 Y lYl finn r r t r t l v v CO 4PUTER DIAGRAM S MPL F ED DIAGRA 4 1 no Y 1 nn PATCHING DIAGRA 4 6 Tmö T 1l o CO 4PUTER DIAGRA SIMFT IFIED DIAGRA 4 1005x 100 ...

Page 117: ...IN yiv ö ö ö lN b to o o 0 OdO O O n o b1ö b o t_t U W 0 l N o o reCre JoLofuslXl lo l Oc1g lXl 0ll I x PATCHING DIAGFA L0Gl 2 ANTTLoG BASE 10 r t toc r o I io LOq olxll x 0 X 1 0 0 roo qc T nn lvl n _ L U _ f0 t0G1elXl PATCHING DIAGRA 4 1 1 1 J r r l l 1 x I J x x l J j ...

Page 118: ... O o O Ly l v E I ö ö T I L v R i t l x ft r 1 t_l o u a O O O O 20 LOGe lXl 50L0G1s lxlx 20lOGe lXl PATCHING DIAGRAI LOG 20 LOGe lXl l AIilIILOG BASE e L0Ge 4o I 0Ge lxlx 5 3 1 086x 20f OGe lxl 50tOG19lxl r ocr fu 50 LoqotxlJ PATCHINGDTAGRAM t r r r r r r r r r r r L t J g ...

Page 119: ...5 MirLTrpLrcATroN rwovnnu ems usrvcrc t55 l_ t_ l__ t l I i i T l t l L _ I l I lr I _r I 1l l r I I XY 1ot t 5 I l I APIENDIX 5 6 Drvrsrow rwo v qnr qsms USINGFG I55 l 3 ...

Page 120: ... X F x SIMTT IF ED DIAGzu 4 TIIE ABOVE O X 5 100 o r 1 0 0 X 0 l oo F x foo DIAGRAMS SHOI I POSITTVE INPUTCIRCUIT ATCHINGDIAGRA 4 OO PUTER DIAGRA 4 L tvrc 20BREAx PorNT g fx F x COMPUTER DIAGRA 4 F X SN IIT IFIED DIAGRA 4 1OO X 100 1oo F x roo PATCHING DIAGRA 4 ...

Page 121: ...TCH NG DIAGRA 4 100 x 100 100 F X 100 S MFT FIEDDIAGRAM 1 7 r r n n n n a 4 tv G l u BRUAKPOINT MONOTONoUS FUNCTIoN Crc o GCrcrc OdO OrO COMPIIIER DIAGRAM PATCH NG D AGR AM 100 X 100 100 F x 100 F X MONoTONOUS DECFEASITT4 trrljlr rT SIM T TF EDDIAGRAM ...

Page 122: ...US FI NCTION e w Crcff wffi gQ lPo ffii3 O O OrO X a n x COI PUTER DIAGRA 4 x or n l x T L F X SIMFT IF NDDIAGRA 4 0 x s 100 or 100 X 0 100 F X tOO TIIE ABOVEDIAGRAMS SH0i l POSIT VE INPUTCIRCUIT PATCHING DTAGRAM F X MONOTONOUS DECREASING FUNCT ON ...

Page 123: ... sirnul ating transfer functions A more complete listing may be found in Jackson A S trAnalog Conputationil McGraw Hill Book Company Inc NewYork 1 60 N0 BODEFT OT TRANSFER IUNCTTON T ts CONSTA IIS GAINS I U 1 I 1 tft L 1 l m 0 K X l rT v T I A K A K l n B A I 1 K v I T l n _ 1 T B 1 4 K T m I I T v I n _ 1 A K B T I n 1 B S I T 7 ...

Page 124: ...iowing table contai irs the shtrrt circuit values for some useful networks for sirnulating mcre extensi ve listing nay be found in Jackson and Fifer S ttAnalog Comprtationfr ad mittance and comPonent transfer f rmctions A A S rrAnalogComPutationrr N0 I D D a rnnm T m Anrf Tmm AlT rE 1UII v rrI A lJl III I livx NETI IOnK t t A R AA P 2 l n I C r F p n 2 I q 1 pT p F iAA 1 AAr I c A 2 R Dal D _ l L ...

Page 125: ...A R l 1 R t R 2 C e R 2 R 1 R 2 6 ATF t t r v r A 1 T r e 1 zRrR a P r r a RrD 2Rr r r g A t R n t u g v r I t r a r 1 r neT Y T l T v e 1 R2 A 2 R 1 T f R J n l v a 2R2 4 2 KI I t n g l v A l T r e 1 n l _ I A 1 n R r I u l fu 2 2cz H v n v f r v z r prr r pt3 A t nt2 T 2 T 1 T 3 H A _L v L R2 C 2 P 2 A 2 R r r K A 1 T 1 R 1 c 1 R r n z l r l l c 1 c z IRr 2R r I r l t g ...

Page 126: ... I T 1 p o T e l_ A R l T t p r p n r L l L r l w A R 2 P r J P A I 1 l r m nr F e 1 RrRr A fr1 R2 D n T l u e 1 2 2 R 1 R 2 r l r 97 t A 1 7 r o l Rr r a p _L D r T P r r r L l t F lnz F 2R2 R1 1 1 o ü I A l r m pr e 1 r R r r u l u 2 a q g i4 u t f u 2 r fr r pt3 _ _l A _ nr2 T 2 S T 1 T 3 _ Ri2 l K T 1 R 1 C 1 n r R z r i l c1 c2 IRi 2R r I ...

Page 127: ...APPENDTX q BANG BANG CIRCUITS 7 l a l 1oo lat Lo r r Vo L o l b l 100 tbl l a l f _ _ l_uLlF a lo Vo 1r Hi 100 b Vo l l o l r 100 O 1 n SOFTL MTTER v l _ ...

Page 128: ...AP ENDIX8 NRO L MIT I ALF I IAVEAECTIFMR 10 11 HYSTEFESIS l_00 l r F2 l ...

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Hitachi 505, Operation Manual

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