Hitachi 15LD2200 User Manual Download

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CAUTION:

Before servicing this chassis, it is important that the service technician read the “Safety

Precautions” and “Product Safety Notices” in this service manual.

ATTENTION:

Avant d’effectuer l’entretien du châassis, le technicien doit lire les «Précautions de sécurité»
et les «Notices de sécurité du produit» présentés dans le présent manuel.

VORSICHT:

Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise
zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.

SERVICE MANUAL
MANUEL D'ENTRETIEN
WARTUNGSHANDBUCH

Data contained within this Service
manual is subject to alteration for
improvement.

Les données fournies dans le présent
manuel d’entretien peuvent faire l’objet
de modifications en vue de perfectionner
le produit.

Die in diesem Wartungshandbuch
enthaltenen Spezifikationen können sich
zwecks Verbesserungen ändern.

SPECIFICATIONS AND PARTS ARE SUBJECT TO CHANGE FOR IMPROVEMENT

Colour Television

September 2004

No. 0208

15LD2200

Summary of Contents for 15LD2200

Page 1: ...Ingenieur die Sicherheitshinweise und Hinweise zurProduktsicherheit indiesemWartungshandbuchzulesen SERVICE MANUAL MANUEL D ENTRETIEN WARTUNGSHANDBUCH Data contained within this Service manual is subject to alteration for improvement Les données fournies dans le présent manuel d entretien peuvent faire l objet de modifications en vue de perfectionner leproduit Die in diesem Wartungshandbuch enthal...

Page 2: ......

Page 3: ...ector PL401 29 3 18 3 S Video Connector JK403 29 3 18 4 LVDS Panel Connector 1x20 PL179 29 3 18 5 TTL Panel Connector Even 2x17 PL177 30 3 18 6 TTL Panel Connector Odd 2x17 PL178 30 3 18 7 Panel Inverter Connector 1x11 PL176 30 3 18 8 Keypad Card Connector 1x5 PL175 31 3 18 9 Optional Keypad Connector to UOC 1x2 PL 202 31 3 18 10 LED IR Receiver Connector 1x6 PL202 31 3 18 11 Optional Rocker Sw Co...

Page 4: ...on Schedule 41 5 2 EEPROM Settings 41 5 2 1 Creating Master EEPROM 41 5 2 2 Creating Mass Production EEPROM 41 5 3 TV Menu 41 5 3 1 Picture Menu 41 5 3 2 Audio Menu 42 5 3 3 Window Menu 42 5 3 4 Options Menu 42 5 3 5 Settings Menu 42 5 4 PC Mode Menu 43 5 4 1 Picture Menu 43 5 4 2 Audio Menü 43 5 4 3 Window Menu 43 5 4 4 Options Menü 43 6 BLOCK DIAGRAM 44 7 CIRCUIT DIAGRAMS 45 7 1 17MB18 Main Boar...

Page 5: ...sted below 1 Full Scart input with SVHS support 1 SVHS input through standard S Video interface 1 CVBS input through standard RCA jack 75 ohms antenna input D Sub 15 PC Input GERMAN NICAM STEREO 3W S B Power Consumption from mains supply 2x3W Speaker Output Power 16 Ohm spks HP Output Stereo Audio line out Stereo Audio line in Equalizer IR Control RC5 OSD Menu Languages ENG FRA GER ITA SPA POR TUR...

Page 6: ...processing there is no need for additional audio processor solution on the board UOC supports three Audio outputs These outputs are assigned to Headphone Speaker and Scart Audio line outputs The board employs TDA7056A and TDA1308 to drive speaker and headphone outputs respectively As another dedicated output for Audio Line out from jack is not possible in UOC this line out signal is obtained by us...

Page 7: ...7 signals A VGA _TV_SW B YUV _TV_SW A B SYNC SOURCE 0 0 UOC 0 1 VGA 1 0 YcbCr 1 1 NOT USED Table 2 H V Sync Multiplexing Table The video output from PW1306 is a 48 bit digital RGB bus format and made available on two separate connectors with TTL control signals i e HS VS CLK etc This digital output is intended to interface to TTL compatible display devices As PW1306 does not have integrated LVDS t...

Page 8: ... TV_VS 74HC14 CTI LTI SANDC MUX BLOCK DAC CS4335 AUDIO AMPLIFIER 2xTDA7056 HP DRIVER TDA1308 V R G B IN PC_ HS VS YCbCr SYNC SEPARATOR EL1883 Y HD_ HS VS PORTD 5 6 58 57 H V SYNC 65 64 R G B AIN 37 43 50 PORTD7 56 D R G B E 0 7 PORTA7 201 DHS DVS DEN DCLK D R G B O 0 7 RGB MACROVISION YUV VGA _SW A H V SYNC LVDS DS90C385 PANEL UOCIII PW1306 PC in RF in Audio in Audio line out CVBS in R G B OUT Com...

Page 9: ...n the volume In menu mode go to right menu item X Connector PL1 on keypads connected to the connector PL175 on the main board Pin No Name Pin No Name 1 Volume 6 Program 2 Volume 7 Program 3 Ground 8 Menu 4 Not Connected 9 TV AV 5 Ground 10 Stand by Shut down Reserved It can be 5V in the future designs if needed 2 3 2 IR Led Board IR LED board contains LED indicator s to show TV s status Red for st...

Page 10: ...400 DDC EEPROM X IC505 MC3416 V3_3A IC203 UOC IC175 Keypad I O IC101 I2C EEPROM X IC502 LM1117 V3_3D IC100 PW1306 IC102 Flash IC176 LVDS X IC500 LM1117 V1_8D IC100 PW1306 X IC501 LM1117 V1_8A IC100 PW1306 X IC504 LM1117 VADC3 IC100 PW1306 X IC503 LM1117 V1_8V1 IC203 UOC X V1_8V2 IC203 UOC X VPP Panel Display Electronics X Table 3 Power management table ...

Page 11: ...9 15 TFT TV Service Manual MC34167 LM1117 LM1117 LM1117 LM1117 LM1117 V3_3D V1_8D V1_8A 12VA VCC5 IRF7314 12V 12V_INV VPP VCC5A or V3_3D or 12VA LM1117 9V VADC3 V3_3A V1_8V1 V1_8V2 VCC5A ...

Page 12: ...ptive digital 4H 2H PAL NTSC combfilter Teletext decoder with 10 page text memory Multi standard stereo decoder BTSC stereo decoder Digital sound processing circuit Digital video processing circuit The UOC III series consists of the following 3 basic concepts Stereo versions These versions contain the TV processor with a stereo audio selector the TCG m Controller the multi standard stereo or BTSC ...

Page 13: ...V VDDA3 3 3V 4 4 4 supply 3 3 V VREF_POS_LSL 5 positive reference voltage SDAC 3 3 V VREF_NEG_LSL HPL 6 negative reference voltage SDAC 0 V VREF_POS_LSR HPR 7 positive reference voltage SDAC 3 3 V VREF_NEG_HPL HPR 8 negative reference voltage SDAC 0 V VREF_POS_HPR 9 positive reference voltage SDAC 3 3 V Figure 6 UOCIII Pin configuration stereo and AV stereo versions with Audio DSP ...

Page 14: ...nput GNDIF 28 28 28 ground connection for IF amplifier SIFIN1 DVBIN1 2 29 29 29 SIF input 1 DVB input 1 SIFIN2 DVBIN2 2 30 30 30 SIF input 2 DVB input 2 AGCOUT 31 31 31 tuner AGC output EHTO 32 32 32 EHT overvoltage protection input AVL SWO SSIF REFO REFIN 2 3 33 33 33 Automatic Volume Levelling switch output sound IF input subcarrier reference output external reference signal input for I signal m...

Page 15: ... C3 59 59 59 chroma 2 3 input AUDOUTLSL 60 62 audio output for audio power amplifier left signal AUDOUTLSR 61 63 audio output for audio power amplifier right signal AUDOUT AMOUT FMOU T 62 audio output AM output FM output volume controlled AUDOUTHPL 62 audio output for headphone channel left signal AUDOUTHPR 63 audio output for headphone channel right signal CVBSO PIP 64 64 64 CVBS PIP output SVM 6...

Page 16: ...e voltage 3 3 V VREFAD 91 reference voltage for audio ADCs 3 3 2 V GNDA 92 92 92 ground VDDA 1 8V 93 93 93 analogue supply for audio ADCs 1 8 V VDDA2 3 3 94 94 94 supply voltage SDAC 3 3 V VSSadc 95 95 95 ground for video ADC and PLL VDDadc 1 8 96 96 96 supply voltage video ADC and PLL INT0 P0 5 97 97 97 external interrupt 0 or port 0 5 4 mA current sinking capability for direct drive of LEDs P1 0...

Page 17: ...26 port 1 2 or external interrupt 2 P1 4 RX 127 127 127 port 1 4 or UART bus P1 5 TX 128 128 128 port 1 5 or UART bus 3 3 PW1306 The PW1306 Video Image Processor is a system on a chip that oversamples and processes RGB or YPbPr video from analog video decoders The PW1306 integrates video processing including deinterlacer and video enhancement filters with a triple ADC Analog RGB or YPbPr in PC gra...

Page 18: ...nction RAIN 37 AI GAIN 43 AI BAIN 50 AI Red Green Blue Analog Inputs These pins receive the Red Green and Blue or YPbPr YCbCr YUV analog signals from the analog video source For proper operation of the clamp feature these inputs must be AC coupled SOGIN 44 AI Analog Sync On Green or Sync On Luma input Allows recovery of the HSYNC signal when this pin is AC coupling to the Green Red or Blue analog ...

Page 19: ...ixel output mode by setting the DCK2EN bit The internal DCLK clock domain can be disabled by the DCLKOFF bit to reduce power consumption DCLKNEG 107 OSR DPort Pixel Clock DVS 101 OS DPort Vertical Sync DVS can be either active high or active low depending on the VSPOL bit Width and timing is controlled by the VPLSE and VDLY registers DHS 102 OS DPort Vertical Sync DHS can be either active high or ...

Page 20: ...ode these pins are the EVEN blue outputs VCLK 72 I O D5 DVPort Pixel Clock The VCLK pin is used for DV port image capture The polarity can be selected by the VCLKPOL bit VPEN 55 I O D5 DVPort Pixel Enable Used when external flow control capture mode is enabled by the EXTFCE bit When VPEN is active the input data is valid The polarity can be selected by the PENPOL bit Use of this pin allows non con...

Page 21: ...hese pins are not used DOG0 121 I O SR5 DOG1 120 I O SR5 DOG2 119 I O SR5 DOG3 118 I O SR5 DOG4 117 I O SR5 DOG5 116 I O SR5 DOG6 115 I O SR5 DOG7 114 I O SR5 DOPort Green Pixel Data In dual pixel output mode these pins are the ODD green outputs In single pixel output mode these pins are not used DOB0 113 I O SR5 DOB1 112 I O SR5 DOB2 111 I O SR5 DOB3 110 I O SR5 DOPort Blue Pixel Data In dual pix...

Page 22: ...e to external ROM CS0 199 I O D5 Miscellaneous Chip Select 0 Low selects external devices CS1 200 I O D5 Miscellaneous Chip Select 1 When EXTRAMEN 0 low selects external devices Chip select for external RAM When EXTRAMEN 1 low selects external RAM RAMCS NMI 194 ID 5 Non Maskable Interrupt A high input triggers a non maskable interrupt to the on chip microprocessor A1 193 I O D5 A2 192 I O D5 A3 19...

Page 23: ...143 I O D5 Microprocessor 16 bit bidirectional data bus PORTA0 208 I O U5 General purpose I O port bit controlled by PADAT0 and PAEN0 This pin has one other possible function when EXTRAMEN 1 When EXTRAMEN 1 and PAEN0 0 PORTA1 is microprocessor address bit 0 A0 PORTA1 207 I O U5 General purpose I O port bit controlled by PADAT1 and PAEN1 This pin has one other possible function when EXTRAMEN 1 When...

Page 24: ...lled by PADAT6 and PAEN6 This pin has one other possible function when PREF1EN 1 When PREF1EN 1 and PAEN6 0 PORTA6 is a variable duty cycle pulse reference generator PWM output controlled by PREF1HI and PREF1LO PORTA7 201 I O D5 General purpose I O port bit controlled by PADAT7 and PAEN7 This pin has one other possible function when PREF0EN 1 When PREF0EN 1 and PAEN7 0 PORTA7 is a variable duty cy...

Page 25: ...generator power VDDPA2 165 P 1 8V analog clock generator power VSSPA1 168 P Clock generator analog ground VSSPA2 166 P Clock generator analog ground PVD 22 24 26 P 1 8V PLL power PGND 21 25 27 P PLL ground DVDD1 1 3 20 P 1 8V ADC digital power DGND1 2 4 19 P ADC digital ground ALVDD 28 29 P 1 8V ADC PLL power ALGND 30 31 P ADC PLL ground AVDD 6 18 32 33 36 39 41 46 48 52 P 3 3V ADC analog power AG...

Page 26: ...GA SVGA XGA and Dual Pixel SXGA Up to 2 38Gbps throughput Up to 297 5 Megabytes sec bandwidth PLL requires no external components Compatible with TIA EIA 644 LVDS standard 3 6 P15V330 The PI5V330 is a true bidirectional Quad 2 channel multiplexer demultiplexer that is for both RGB and composite video switching applications 200MHz bandwidth 3 Ohm on resistance Switching at 10 ns 100 mA output curre...

Page 27: ...0 TDA1308 The TDA1308 is an integrated class AB stereo headphone driver contained in an SO8 DIP8 or a TSSOP8 plastic package Wide temperature range No switch on off clicks Low power consumption Short circuit resistant PIN SYMBOL DESCRIPTION PIN VALUE 1 OUTA Output A Voltage swing Min 0 75V Max 4 25V 2 INA neg Inverting input A Vo clip Min 1400mVrms 3 INA pos Non inverting input A 2 5V 4 VSS Negati...

Page 28: ...al Protection Output Current 800mA Line Regulation 0 2 Max Load Regulation 0 4 Max Temperature Range LM1117 0 C to 125 C LM1117I 40 C to 125 C 3 12 24LC32 24LC32 is a 4K x 8 32Kbit Serial Electrically Erasable PROM capable of operation across a broad voltage range 2 5V to 6 0V 3 13 24LC21 24LC21 is a 128 x 8 bit Electrically Erasable PROM This device is designed for use in applications requiring s...

Page 29: ...ply and a large debounce time are expected The device can generate 2048 different commands and utilizes a keyboard with a single pole switch for each key The commands are arranged so that 32 systems can be addressed each system containing 64 different commands The circuit response to legal one key pressed at a time and illegal more than one key pressed at a time keyboard operation is specified in ...

Page 30: ...lso included is a low power standby mode that reduces power supply current to 36mA Output Switch Current in Excess of 5 0A Fixed Frequency Oscillator 72kHz with On Chip Timing Provides 5 05V Output without External Resistor Divider Precision 2 Reference 0 to 95 Output Duty Cycle Cycle by Cycle Current Limiting Under voltage Lockout with Hysteresis Internal Thermal Shutdown Operation from 7 5V to 4...

Page 31: ... switching control High 1 3V RGB Low 0 0 4V Composite 75ohms 17 Ground video input output 18 Ground RGB switching control 19 CVBSO2 Video output composite 1V including sync 75ohms 20 Y1SCART Video input composite or Luminance input 1V including sync 75ohms 21 Common ground shield 3 18 3 S Video Connector JK403 Pin Signal Impedance 1 Ground 2 Ground 3 Luminance 75Ω 4 Chrominance 75Ω 3 18 4 LVDS Pan...

Page 32: ...K 17 DGE1 Green 34 DCLK 3 18 6 TTL Panel Connector Odd 2x17 PL178 Pin Symbol Description Pin Symbol Description 1 DBO7 Blue 18 DGO1 Green 2 DBO6 Blue 19 DGO0 Green 3 DBO5 Blue 20 GND Ground 4 DBO4 Blue 21 DRO7 Red 5 GND Ground 22 DRO6 Red 6 DBO3 Blue 23 DRO5 Red 7 DBO2 Blue 24 DRO4 Red 8 DBO1 Blue 25 GND Ground 9 DBO0 Blue 26 DRO3 Red 10 GND Ground 27 DRO2 Red 11 DGO7 Green 28 DRO1 Red 12 DGO6 Gre...

Page 33: ...500 3 4 Switched 12V 3 18 12 PROMJet Connector 2x25 PL101 Pin Symbol Description Pin Symbol Description 1 2 NC Not connected 27 28 A 15 16 Address 3 A 1 Address 29 30 A 13 14 Address 4 V3_3D Digital 3 3V 31 32 A 11 12 Address 5 GND 33 34 A 9 10 Address 6 ROMOE ROM output enable 35 36 37 NC Not connected 7 9 11 13 D 0 3 Data 38 ROMWE ROM write enable 8 10 12 14 D 8 11 Data 39 V3_3D Digital 3 3V 15 ...

Page 34: ...14 Side AV Connector for Side card Option PL406 Pin Signal Pin Signal 1 Ground 4 Right Audio in 2 Left Audio in 5 Ground 3 Ground 6 CVBS in 3 18 15 Side SVHS Connector for Side card Option PL407 Pin Signal 1 Y Luma 2 Ground 3 C Chroma ...

Page 35: ...GTV 3 2 1 00XXX 1 Init TV Sets the UOC default values and turns the tv to Stdby GTV 3 2 1 0 2 ISP Mode Sets the TV into ISP state GTV 3 2 1 0 3 DCXO DCXO crystal alignment Crystal alignment 70 4 DCXO Auto Automatic DCXO frequency alignment When it is set to 1 UOC automaticaly calculates DCXO values and writes it to item number 3 Crystal alignment 0 5 Track mode Geometry 0 6 Hor Shift Geometry 32 7...

Page 36: ...akRatioOvShot Video 2 45 Tint NTSC Video 31 46 OSO Bit Control 0 47 FSL Bit Control 0 48 HP2 Bit Control 0 49 SoftClipLevel Bit Control 0 50 OP AUDIO CONFIG Audio options 2 51 OP BILING Audio options 1 52 OP HP Audio options 1 53 OP EQUAL Audio options 1 54 OP DOLBY Audio options 0 55 OP TRUSUR Audio options 0 56 OP DUB DBE Audio options 0 57 OP BBE Audio options 0 58 AVL LEV AVL level setting Aud...

Page 37: ...et 55 95 PA B4 VO Audio Preset 45 96 PA B5 VO Audio Preset 34 97 PA BA MU Audio Preset 34 98 PA TR MU Audio Preset 39 99 PA LM MU Audio Preset 1 100 PA ST MU Audio Preset 5 101 PA LO MU Audio Preset 1 102 PA B1 MU Audio Preset 52 103 PA B2 MU Audio Preset 47 104 PA B3 MU Audio Preset 29 105 PA B4 MU Audio Preset 29 106 PA B5 MU Audio Preset 45 107 PA BA TH Audio Preset 36 108 PA TR TH Audio Preset...

Page 38: ...XT ON Teletext options 1 143 TXT SPLIT Teletext options 1 144 TXT H POS Teletext options 11 145 TIM REM Timer options 1 146 TIM SLP Timer options 1 147 TIM SW Timer options 1 148 TIM OFF Timer options 1 149 TIM SKP Timer options 1 150 TIM RT Timer options 1 151 FM Radio FM Radio options 1 152 PWR SAVING Power options 1 153 PWR PERF Power options 3 154 PWR REST Power options 0 155 PWR ONKEY Power o...

Page 39: ...ed above and go to AGC Take over setting by pressing 1 1 8 Measure AGC voltage from Tuner Pin1 By pressing Volume adjust AGC voltage so that the measured value at this step should be 0 5V less than the value measured at first step Around 3 5V 4 1 3 DCXO Alignment If this alignment has not properly been done some front end RF problems can be observed such as Nicam stereo mono sound switching low RF...

Page 40: ...4 2 2 UOC Calibration Apply 11 Vertical bar Grey scale pattern with black on the left and white on the right side of the picture as seen below from CVBS input Press RC AV button and switch to CVBS input and observe the pattern applied Enter to PW1306 service menu Press RC DOWN button at Service Submenu 1 and highlight UOC Calibration Press RC RIGHT button to start calibration 4 2 3 PW1306 PC Input...

Page 41: ... buttons to set Hotel Mode to on or off 4 2 7 Burn In Mode Press RC RIGHT button at Service Submenu 1 and switch to Service Submenu 2 Press RC DOWN button and highlight Hotel Mode Press RC RIGHT and LEFT buttons to set Burn In Mode to on or off 4 2 8 Country Press RC RIGHT button at Service Submenu 1 and switch to Service Submenu 2 Press RC RIGHT button at Service Submenu 2 and switch to Factory S...

Page 42: ...u background to opaque or translucent 4 2 12 Remote Control Press RC RIGHT button at Service Submenu 1 and switch to Service Submenu 2 Press RC RIGHT button at Service Submenu 2 and switch to Factory Settings Press RC DOWN button and highlight Remote Control Press RC RIGHT and LEFT buttons to set the desired remote control option 4 2 13 PC Mode Press RC RIGHT button at Service Submenu 1 and switch...

Page 43: ...tically assign the initial values to the EEPROM Adjust the settings of Service Menu and User Menu This EEPROM can be used as Master EEPROM 5 2 2 Creating Mass Production EEPROM The Master EEPROM prepared like above is copied and multiplied to use in mass production The copy EEPROM is placed on IC 101 of 17MB18 When TV is turned on the software will realise that EEPROM is not empty so SW will not c...

Page 44: ...mage size auto white tone normal dynamic skin tone off 5 3 4 Options Menu Options menu background opaque Language room lighting bright sleep time 0 child lock off Will be changed according to the DI 5 3 5 Settings Menu Installation Channel Setup APS program number country program name aps manual search standard Auto store frequency fine tuning program skip Off teletext language Europe teletext reg...

Page 45: ... is no need to adjust any value in this section 5 4 2 Audio Menu Audio volume 29 balance 49 AVL on extended audio features Feature headphone Equilizer Effect normal volume 10 sound style user balance 49 Will be left unchanged as they are adjusted in the EEPROM 5 4 3 Window Menu Window H Position 50 V Position 50 5 4 4 Options Menu Options menu background opaque Language room lighting normal auto a...

Page 46: ...1308 TDA7056A Line PC in SAW P A N E L S video in Audio RF Audio In L R RGB TA1366 LTI CTI YUV out YUV in RGB FB RGB Scart DAC I2S PI5 V330 Optional YCbCr input FBLIN Side Optional YCbCr input from scart PI5 V330 YUV_TV_SW VGA_TV_ SW DRGB 24 DEN DCLK DVS DHS TTL 48 ...

Page 47: ...45 15 TFT TV Service Manual 7 CIRCUIT DIAGRAMS 7 1 17MB18 Main Board Schematics 17MB18 2 001 ...

Page 48: ...46 15 TFT TV Service Manual 17MB18 2 002 ...

Page 49: ...47 15 TFT TV Service Manual 17MB18 2 003 ...

Page 50: ...48 15 TFT TV Service Manual 17MB18 2 004 ...

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Page 52: ...50 15 TFT TV Service Manual 7 2 Keypad Schematics 17TKXX ...

Page 53: ...51 15 TFT TV Service Manual 7 3 IR LED Board Schematics 17LDXX ...

Page 54: ...52 15 TFT TV Service Manual 7 4 Remote Controller Schematics 11UK10 2 ...

Page 55: ...QTY DESCRIPTION NO ...

Page 56: ...PWB INVERTER BOARD VS30018343 PWB MAIN 17MB18 VS20197129 PWB LED BOARD 17LD01C VS20198184 PWB KEY BOARD 17KT16 5SW VS20168791 ...

Page 57: ...THE UPDATED PARTS LIST FOR THIS MODEL IS AVAILABLE ON ESTA ...

Page 58: ...47 Milano Italia ITALY Tel 39 02 487861 Tel 39 02 38073415 Servizio Clienti Fax 39 02 48786381 2 Email customerservice italy hitachi eu com HITACHI Europe AB Box 77 S 164 94 Kista SWEDEN Tel 46 0 8 562 711 00 Fax 46 0 8 562 711 13 Email csgswe hitachi eu com HITACHI EUROPE S A S Lyon Office B P 45 69671 BRON CEDEX FRANCE Tel 33 04 72 14 29 70 Fax 33 04 72 14 29 99 Email france consommateur hitachi...

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