Epson ARM720T Core cpu User Manual Download

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ARM720T Revision 4

(AMBA AHB Bus Interface Version)

CORE CPU MANUAL

EPSON Electronic Devices Website

ELECTRONIC DEVICES MARKETING DIVISION

http://www.epsondevice.com

Issue April, 2004

Printed in Japan

Document code: 405003400

CORE CPU MANUAL

ARM720T Revision 4

(AMBA AHB Bus Interface Version)

CORE CPU MANUAL

ARM720T Revision 4

(AMBA AHB Bus Interface Version)

Summary of Contents for ARM720T Core cpu

Page 1: ...ronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http www epsondevice com Issue April 2004 Printed in Japan C A Document code 405003400 CORE CPU MANUAL ARM720T Revision 4 AMBA AHB Bus Interface Version CORE CPU MANUAL ARM720T Revision 4 AMBA AHB Bus Interface Version ...

Page 2: ... implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licen...

Page 3: ...mer s Model 3 Configuration 4 Instruction and Data Cache 5 Write Buffer 6 The Bus Interface 7 Memory Management Unit 8 Coprocessor Interface 9 Debugging Your System 10 ETM Interface 11 Test Support A Signal Descriptions Glossary Index ...

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Page 5: ...l addresses by the FCSE PID 2 15 2 10 Reset 2 16 2 11 Implementation defined behavior of instructions 2 17 3 Configuration 3 1 About configuration 3 1 3 2 Internal coprocessor instructions 3 2 3 3 Registers 3 3 4 Instruction and Data Cache 4 1 About the instruction and data cache 4 1 4 2 IDC validity 4 2 4 3 IDC enable disable and reset 4 2 5 Write Buffer 5 1 About the write buffer 5 1 5 2 Write b...

Page 6: ... About debugging your system 9 2 9 2 Controlling debugging 9 3 9 3 Entry into debug state 9 5 9 4 Debug interface 9 9 9 5 ARM720T core clock domains 9 9 9 6 The EmbeddedICE RT macrocell 9 10 9 7 Disabling EmbeddedICE RT 9 11 9 8 EmbeddedICE RT register map 9 12 9 9 Monitor mode debugging 9 12 9 10 The debug communications channel 9 14 9 11 Scan chains and the JTAG interface 9 17 9 12 The TAP contr...

Page 7: ...ing 10 3 11 Test Support 11 1 About the ARM720T test registers 11 1 11 2 Automatic Test Pattern Generation ATPG 11 2 11 3 Test State Register 11 3 11 4 Cache test registers and operations 11 3 11 5 MMU test registers and operations 11 8 A Signal Descriptions A 1 AMBA interface signals A 1 A 2 Coprocessor interface signals A 2 A 3 JTAG and test signals A 3 A 4 Debugger signals A 4 A 5 Embedded trac...

Page 8: ... Figure 3 11 PROCID Register format 3 8 Figure 6 1 Simple AHB transfer 6 2 Figure 6 2 AHB bus master interface 6 4 Figure 6 3 Simple memory cycle 6 5 Figure 6 4 Transfer type examples 6 6 Figure 7 1 Translation Table Base Register 7 4 Figure 7 2 Translating page tables 7 5 Figure 7 3 Accessing translation table level one descriptors 7 6 Figure 7 4 Level one descriptor 7 6 Figure 7 5 Section descri...

Page 9: ...9 16 Debug status register format 9 41 Figure 9 17 Debug control and status register structure 9 42 Figure 11 1 CP15 MRC and MCR bit pattern 11 1 Figure 11 2 Rd format CAM read 11 4 Figure 11 3 Rd format CAM write 11 4 Figure 11 4 Rd format RAM read 11 5 Figure 11 5 Rd format RAM write 11 5 Figure 11 6 Rd format CAM match RAM read 11 5 Figure 11 7 Data format CAM read 11 5 Figure 11 8 Data format ...

Page 10: ... Active byte lanes for a 32 bit little endian data bus 6 11 Table 6 7 Active byte lanes for a 32 bit big endian data bus 6 12 Table 7 1 CP15 register functions 7 3 Table 7 2 Level one descriptor bits 7 7 Table 7 3 Interpreting level one descriptor bits 1 0 7 7 Table 7 4 Section descriptor bits 7 8 Table 7 5 Coarse page table descriptor bits 7 9 Table 7 6 Fine page table descriptor bits 7 9 Table 7...

Page 11: ...c7 c9 and c15 operations 11 4 Table 11 4 Write cache victim and lockdown operations 11 6 Table 11 5 CAM RAM1 and RAM2 register c15 operations 11 9 Table 11 6 Register c2 c3 c5 c6 c8 c10 and c15 operations 11 9 Table 11 7 CAM memory region size 11 10 Table 11 8 Access permission bit setting 11 11 Table 11 9 Miss and fault encoding 11 11 Table 11 10 RAM2 memory region size 11 12 Table A 1 AMBA inter...

Page 12: ...CONTENTS viii EPSON ARM DDI 0229B THIS PAGE IS BLANK ...

Page 13: ...Preface ...

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Page 15: ...organized into the following chapters Chapter 1 Introduction Read this chapter for an introduction to the ARM720T processor Chapter 2 Programmer s Model Read this chapter for a description of the 32 bit ARM and 16 bit Thumb instruction sets Chapter 3 Configuration Read this chapter for a description of the ARM1156F S control coprocessor CP15 register configurations and programming details Chapter ...

Page 16: ...ions are used in this document bold Highlights ARM processor signal names and interface elements such as menu names Also used for terms in descriptive lists where appropriate italic Highlights special terminology cross references and citations monospace Denotes text that can be entered at the keyboard such as commands file names and program names and source code monospace Denotes a permitted abbre...

Page 17: ...enda and ARM Frequently Asked Questions ARM publications This document contains information that is specific to the ARM720T processor Refer to the following documents for other relevant information ARM Architecture Reference Manual ARM DDI 0100 AMBA Specification Rev 2 0 ARM IHI 0011 ETM7 Rev 1 Technical Reference Manual ARM DDI 0158 ARM7TDMI S Rev 4 Technical Reference Manual ARM DDI 0234 Other p...

Page 18: ...Preface xiv EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 19: ...1 Introduction ...

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Page 21: ...ions and sophisticated operating systems The allocation of virtual addresses with different task IDs improves performance in task switching operations with the cache enabled These relocated virtual addresses are monitored by the EmbeddedICE RT block The memory interface enables the performance potential to be realized without incurring high costs in the memory system Speed critical control signals...

Page 22: ...hown in Figure 1 1 Figure 1 1 720T Block diagram MMU Data and address buffers AMBA interface 8KB cache Control and clocking logic ARM720T core System control coprocessor Virtual address bus AMBA AHB bus interface JTAG debug interface ETM interface Coprocessor interface Internal data bus ARM720T ...

Page 23: ...e EmbeddedICE RT logic contains a Debug Communications Channel DCC The DCC is used to pass information between the target and the host debugger The EmbeddedICE RT logic is controlled through the Joint Test Action Group JTAG test access port ARM720T processor HADDR 31 0 EXTCPDBE CPnMREQ CPnTRANS CPTBIT CPnOPC CPnCPI EXTCPB EXTCPA EXTCPDOUT 31 0 EXTCPDIN 31 0 EXTCPCLKEN HRESETn HCLKEN HLOCK HBUSREQ ...

Page 24: ...rs debug state Bit 5 EmbeddedICE RT disable Use this when changing watchpoints and breakpoints When set this bit disables breakpoints and watchpoints enabling the breakpoint or watchpoint registers to be programmed with new values When clear the new breakpoint or watchpoint values become operational For more information see Debug control register on page 9 39 Coprocessor register map A new registe...

Page 25: ...rel shifter and multiplier to perform high speed operations on the data in a bank of 31 registers each 32 bits wide Three types of instruction control the data transfer between memory and the registers one optimized for flexibility of addressing one for rapid context switching one for swapping data Two instructions control the flow and privilege level of execution Three types are dedicated to the ...

Page 26: ...cription cond Refer to Table 1 11 on page 1 13 Oprnd2 Refer to Table 1 9 on page 1 12 field Refer to Table 1 10 on page 1 12 S Sets condition codes optional B Byte operation optional H Halfword operation optional T Forces address translation Cannot be used with pre indexed addresses a_mode2 Refer to Table 1 3 on page 1 10 a_mode2P Refer to Table 1 4 on page 1 11 a_mode3 Refer to Table 1 5 on page ...

Page 27: ...n op1 op1 swi_number L Rn RdLo Rd Rd Register list Rs CRn CRn CRd CRd Rd cp_num cp_num cp_num Rn 1 0 0 1 1 0 0 1 SBZ 1 S H 1 High offset 1 S H 1 Rm Rm Rm Rm Low offset 8_bit_offset op2 op2 0 1 CRm CRm 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Data pr...

Page 28: ... Subtract with carry SBC cond S Rd Rn Oprnd2 Subtract reverse subtract RSB cond S Rd Rn Oprnd2 Subtract reverse subtract with carry RSC cond S Rd Rn Oprnd2 Multiply MUL cond S Rd Rm Rs Multiply accumulate MLA cond S Rd Rm Rs Rn Multiply unsigned long UMULL cond S RdLo RdHi Rm Rs Multiply unsigned accumulate long UMLAL cond S RdLo RdHi Rm Rs Multiply signed long SMULL cond S RdLo RdHi Rm Rs Multipl...

Page 29: ...M cond a_mode4L Rd reglist Stack operations and restore CPSR LDM cond a_mode4L Rd reglist pc User registers LDM cond a_mode4L Rd reglist Store Word STR cond Rd a_mode2 Word with User Mode privilege STR cond T Rd a_mode2P Byte STR cond B Rd a_mode2 Byte with User Mode privilege STR cond BT Rd a_mode2P Halfword STR cond H Rd a_mode3 Multiple block data operations Increment before STM cond IB Rd regl...

Page 30: ...set Register offset Rn Rm Scaled register offset Rn Rm LSL 5bit_shift_imm Rn Rm LSR 5bit_shift_imm Rn Rm ASR 5bit_shift_imm Rn Rm ROR 5bit_shift_imm Rn Rm RRX Pre indexed immediate offset Rn 12bit_Offset Pre indexed register offset Rn Rm Pre indexed scaled register offset Rn Rm LSL 5bit_shift_imm Rn Rm LSR 5bit_shift_imm Rn Rm ASR 5bit_shift_imm Rn Rm ROR 5bit_shift_imm Rn Rm RRX Post indexed imme...

Page 31: ... Rn Rm ROR 5bit_shift_imm Rn Rm RRX Post indexed immediate offset Rn 12bit_Offset Post indexed register offset Rn Rm Post indexed scaled register offset Rn Rm LSL 5bit_shift_imm Rn Rm LSR 5bit_shift_imm Rn Rm ASR 5bit_shift_imm Rn Rm ROR 5bit_shift_imm Rn Rm RRX Table 1 5 Addressing mode 3 Operation Assembler Immediate offset Rn 8bit_Offset Pre indexed Rn 8bit_Offset Post indexed Rn 8bit_Offset Re...

Page 32: ...ending Table 1 8 Addressing mode 5 Operation Assembler Immediate offset Rn 8bit_Offset 4 Pre indexed Rn 8bit_Offset 4 Post indexed Rn 8bit_Offset 4 Table 1 9 Operand 2 Operation Assembler Immediate value 32bit_Imm Logical shift left Rm LSL 5bit_Imm Logical shift right Rm LSR 5bit_Imm Arithmetic shift right Rm ASR 5bit_Imm Rotate right Rm ROR 5bit_Imm Register Rm Logical shift left Rm LSL Rs Logica...

Page 33: ...ned lower C clear MI Negative N set PL Positive or zero N clear VS Overflow V set VC No overflow V clear HI Unsigned higher C set Z clear LS Unsigned lower or same C clear Z set GE Greater or equal N V N and V set or N and V clear LT Less than N V N set and V clear or N clear and V set GT Greater than Z clear N V N and V set or N and V clear LE Less than or equal Z set or N V N set and V clear or ...

Page 34: ... 1 L 1 0 0 Rd Word8 0 SP 1 0 1 SWord7 0 0 0 S 1 1 0 1 0 Rlist 1 0 R 1 1 L 1 0 Rlist Rb 0 0 L 1 1 Softset8 Cond 0 1 1 1 Value8 1 1 1 1 1 0 1 1 Offset11 0 1 1 0 1 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 03 04 06 02 05 07 08 09 10 11 12 13 14 15 16 17 18 19 Move shifted register Move compare add and subtract immediate ALU operation High register operations and branch exchange PC relative load...

Page 35: ... Hd Rs Add High to High ADD Hd Hs Add Immediate ADD Rd 8bit_Imm Add Value to SP ADD SP 7bit_Imm ADD SP 7bit_Imm Add with carry ADC Rd Rs Subtract SUB Rd Rs Rn SUB Rd Rs 3bit_Imm Subtract Immediate SUB Rd 8bit_Imm Subtract with carry SBC Rd Rs Negate NEG Rd Rs Multiply MUL Rd Rs Compare Low and Low CMP Rd Rs Compare Low and High CMP Rd Hs Compare High and Low CMP Hd Rs Compare High and High CMP Hd ...

Page 36: ... label if C set and Z clear BHI label if C clear and Z set BLS label if N set and V set or if N clear and V clear BGE label if N set and V clear or if N clear and V set BLT label if Z clear and N or V set or if Z clear and N or V clear BGT label if Z set or N set and V clear or N clear and V set BLE label Unconditional B label Long branch with link BL label Optional state change to address held in...

Page 37: ...fset using SP ADD Rd SP 10bit_offset Multiple LDMIA Rb reglist Store With immediate offset word STR Rd Rb 7bit_offset halfword STRH Rd Rb 6bit_offset byte STRB Rd Rb 5bit_offset With register offset word STR Rd Rb Ro halfword STRH Rd Rb Ro byte STRB Rd Rb Ro SP relative STR Rd SP 10bit_offset Multiple STMIA Rb reglist Push Pop Push registers onto stack PUSH reglist Push LR and registers onto stack...

Page 38: ...0T CORE CPU MANUAL 1 4 Silicon revisions This manual is for revision r4p2 of the ARM720T macrocell See Product revision status on page xii for details of revision numbering There are no functional differences from previous revisions ...

Page 39: ...2 Programmer s Model ...

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Page 41: ... instructions In this state the PC uses bit 1 to select between alternate halfwords 2 1 1 Switching between processor states Transition between processor states does not affect the processor mode or the contents of the registers Entering Thumb state Entry into Thumb state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to Thumb state al...

Page 42: ...status of the B bit in the Control Register of the system control coprocessor See Control Register on page 3 4 for more information 2 2 1 Big endian format In big endian format the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte Byte 0 of the memory system is therefore connected to data lines 31 to 24 Big endian form...

Page 43: ...ses of bytes with words Note Least significant byte is at lowest address Word is addressed by byte address of least significant byte 2 3 Instruction length Instructions are 32 bits long in ARM state 16 bits long in Thumb state 2 4 Data types The ARM720T processor supports the following data types byte 8 bit halfword 16 bit word 32 bit You must align these as follows word quantities to 4 byte bound...

Page 44: ...al purpose and can be used to hold either data or address values Registers r14 and r15 also have special roles as follows Register r14 This register is used as the subroutine Link Register This receives a copy of r15 when a Branch and Link BL code instruction is executed At all other times it can be treated as a general purpose register The corresponding banked registers r14_svc r14_irq r14_fiq r1...

Page 45: ...organization in ARM state ARM state general registers and program counter r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 PC System and User CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und ARM state program status registers banked register r0 r1 r2 r3 r4 r5 r6 r7 r8_fiq r9_fiq r10_fiq r11_fiq r12_fiq r13_fiq r14_fiq r15 PC FIQ r0 r1 r2 r3 r4 r5 r6 r7 r13_svc r14_sv...

Page 46: ...leged mode This is shown in Figure 2 4 Figure 2 4 Register organization in Thumb state Thumb state general registers and program counter System and User r0 r1 r2 r3 r4 r5 r6 r7 SP LR PC CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und Thumb state program status registers banked register FIQ r0 r1 r2 r3 r4 r5 r6 r7 SP_fiq LR_fiq PC Supervisor r0 r1 r2 r3 r4 r5 r6 r7 SP_svc...

Page 47: ...ers in Thumb state In Thumb state ARM registers r8 r15 the high registers are not part of the standard register set However the assembly language programmer has limited access to them and can use them for fast temporary storage A value can be transferred from a register in the range r0 r7 a low register to a high register and from a high register to a low register using special variants of the MOV...

Page 48: ... control bits These change when an exception arises If the processor is operating in a privileged mode they can also be manipulated by software I and F bits These are the interrupt disable bits When set these disable the IRQ and FIQ interrupts respectively The T bit This reflects the operating state When this bit is set the processor is executing in Thumb state otherwise it is executing in ARM sta...

Page 49: ...Visible ARM state registers b10000 User r7 to r0 LR SP PC CPSR r14 to r0 PC CPSR b10001 FIQ r7 to r0 LR_fiq SP_fiq PC CPSR SPSR_fiq r7 to r0 r14_fiq r8_fiq PC CPSR SPSR_fiq b10010 IRQ r7 to r0 LR_irq SP_irq PC CPSR SPSR_irq r12 to r0 r14_irq r13_irq PC CPSR SPSR_irq b10011 Supervisor r7 to r0 LR_svc SP_svc PC CPSR SPSR_svc r12 to r0 r14_svc r13_svc PC CPSR SPSR_svc b10111 Abort r7 to r0 LR_abt SP_...

Page 50: ...sor behaves as follows 1 It preserves the address of the next instruction in the appropriate LR a If the exception has been entered from ARM state the address of the next instruction is copied into the LR that is current PC 4 or PC 8 depending on the exception See Table 2 3 on page 2 11 for details b If the exception has been entered from Thumb state the value written into the LR is the current PC...

Page 51: ...C value preserved in the relevant r14 register on exception entry and the recommended instruction for exiting the exception handler Table 2 3 Exception entry and exit Exception Return instruction Previous state ARM r14_x Thumb r14_x BLa a PC is the address of the BL SWI Undefined Instruction or Fetch that had the Prefetch Abort MOV PC r14 PC 4 PC 2 SWIa MOVS PC r14_svc PC 4 PC 2 UDEFa MOVS PC r14_...

Page 52: ...whether the exception was entered from ARM or Thumb state an IRQ handler must return from the interrupt by executing SUBS PC r14_irq 4 2 8 6 Abort An abort indicates that the current memory access cannot be completed It can be signaled either by the protection unit or by the HRESP bus The ARM720T processor checks for the abort exception during memory access cycles There are two types of abort as f...

Page 53: ...ined Instruction trap This mechanism can be used to extend either the Thumb or ARM instruction set by software emulation After emulating the failed instruction the trap handler must execute the following irrespective of the state ARM or Thumb MOVS PC r14_und This restores the CPSR and returns to the instruction following the Undefined Instruction 2 8 9 Exception vectors The ARM720T processor can h...

Page 54: ...y exclusive because they each correspond to particular non overlapping decodings of the current instruction If a Data Abort occurs at the same time as an FIQ and FIQs are enabled the CPSR F flag is clear the ARM720T processor enters the Data Abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ causes the Data Abort handler to resume execution Placing Data Abort at...

Page 55: ...o the FCSE PID exhibits similar behavior to a delayed branch if the two instructions fetched immediately following an instruction to change the FCSE PID are fetched with a relocation to the previous FCSE PID the addresses of the instructions being fetched lie within the range of addresses to be relocated On reset the FCSE PID register bits 31 25 are set to b0000000 disabling all relocation For thi...

Page 56: ...ut and stores the result in the V bit in CP15 register 1 When HRESETn goes HIGH again the ARM720T processor 1 Overwrites r14_svc and SPSR_svc by copying the current values of the PC and CPSR into them The value of the saved PC and SPSR is not defined 2 Forces M 4 0 to b10011 Supervisor mode sets the I and F bits in the CPSR and clears the CPSR T bit 3 Forces the PC to fetch the next instruction fr...

Page 57: ...nation for those features that define signed and unsigned early termination on the ARM720T processor 2 11 1 Indexed addressing on a Data Abort In the event of a Data Abort with pre indexed or post indexed addressing the value left in Rn is defined to be the updated base register value for the following instructions LDC LDM LDR LDRB LDRBT LDRH LDRSB LDRSH LDRT STC STM STR STRB STRBT STRH STRT 2 11 ...

Page 58: ...2 Programmer s Model 2 18 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 59: ...3 Configuration ...

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Page 61: ...ion options 3 1 1 Compatibility To ensure backwards compatibility of future CPUs all reserved or unused bits in registers and coprocessor instructions must be programmed to 0 invalid registers must not be read or written the following bits must be programmed to 0 Register 1 bits 31 14 and bits 12 10 Register 2 bits 13 0 Register 5 bits 31 9 Register 7 bits 31 0 Register 13 FCSE PID bits 24 0 3 1 2...

Page 62: ...R instructions in a privileged mode The instruction bit pattern of the MRC and MCR instructions is shown in Figure 3 1 Figure 3 1 MRC and MCR bit pattern CDP LDC and STC instructions as well as unprivileged MRC and MCR instructions to CP15 cause the Undefined Instruction trap to be taken The CRn field of MRC and MCR instructions specifies the coprocessor register to access The CRm field and opcode...

Page 63: ...table ID Register write format is shown in Figure 3 3 Figure 3 3 ID Register write format Table 3 1 Cache and MMU Control Register Register Register reads Register writes 0 ID Register Reserved 1 Control Register Control Register 2 Translation Table Base Register Translation Table Base Register 3 Domain Access Control Register Domain Access Control Register 4 Reserved Reserved 5 Fault Status Regis...

Page 64: ...disabled 1 MMU enabled A Bit 1 Alignment fault enable disable 0 Address Alignment Fault Checking disabled 1 Address Alignment Fault Checking enabled C Bit 2 Cache enable disable 0 Instruction and or Data Cache IDC disabled 1 Instruction and or Data Cache IDC enabled W Bit 3 Write buffer enable disable 0 Write Buffer disabled 1 Write Buffer enabled P Bit 4 When read returns 1 When written is ignore...

Page 65: ...n be considered as a branch with delayed execution A similar situation occurs when the MMU is disabled The correct code sequence for enabling and disabling the MMU is given Interaction of the MMU and cache on page 7 21 Note When the MMU is disabled the Cache is disabled If the cache and write buffer are enabled when the MMU is not enabled the results are Unpredictable 3 3 3 Translation Table Base ...

Page 66: ...SR indicates the domain and type of access being attempted when an abort occurred Bit 8 This is always read as zero Bit 8 is ignored on writes Bits 7 4 These specify which of the 16 domains D15 D0 was being accessed when a fault occurred Bits 3 1 These indicate the type of access being attempted The encoding of these bits is shown in Fault address and fault status registers on page 7 16 The FAR is...

Page 67: ...ng opcode_2 and CRm fields in the MCR instruction that writes the CP15 Register 7 Caution The Invalidate ID cache function invalidates all cache data Use this with caution Register 7 is shown in Table 3 2 Reading from CP15 Register 7 is undefined 3 3 8 TLB Operations Register Writing to CP15 Register 8 controls the Translation Lookaside Buffer TLB The ARM720T processor implements a unified instruc...

Page 68: ...e returned The remaining 25 bits are Unpredictable Writing to CP15 Register 13 with opcode_2 0 updates the FCSE PID from the value in bits 31 25 Bits 24 0 Should Be Zero The FCSE PID is set to b0000000 on Reset The CRm and opcode_2 Should Be Zero when reading or writing the FCSE PID Changing FCSE PID You must take care when changing the FCSE PID because the following instructions have been fetched...

Page 69: ...SON 3 9 3 3 10 Register 14 reserved Accessing this register is undefined Writing to Register 14 is Undefined 3 3 11 Test Register The CP15 Register 15 is used for device specific test operations For more information see Chapter 11 Test Support ...

Page 70: ...3 Configuration 3 10 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 71: ...4 Instruction and Data Cache ...

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Page 73: ...owever you can enable the two devices simultaneously with a single write to the Control Register see Control Register on page 3 4 4 1 2 Cachable bit The C bit determines if data being read can be placed in the IDC and used for subsequent read operations Typically main memory is marked as cachable to improve system performance and I O space is marked as noncachable to stop the data being stored in ...

Page 74: ...uction fetches can come from the cache before the register is written 4 2 2 Doubly mapped space Because the cache works with virtual addresses it is assumed that every virtual address maps to a different physical address If the same physical location is accessed by more than one virtual address the cache cannot maintain consistency Each virtual address has a separate entry in the cache and only on...

Page 75: ...5 Write Buffer ...

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Page 77: ...Bufferable B bit which is stored in the MMU page tables For this reason the MMU must be enabled before using the write buffer The two functions can however be enabled simultaneously with a single write to the Control Register For a write to use the write buffer both the W bit in the Control Register and the B bit in the corresponding page table must be set Note It is not possible to abort buffered...

Page 78: ...n the write buffer at the speed of HCLK and the CPU continues execution The write buffer then performs the external write in parallel If the write buffer is full the processor is stalled until there is an empty line in the buffer 5 2 2 Unbufferable write If the write buffer is disabled or the CPU performs a write to an unbufferable area the processor is stalled until the write buffer empties and t...

Page 79: ...6 The Bus Interface ...

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Page 81: ...ommended that you use fully AMBA compliant peripherals and interfaces early in your design cycle The AHB timings described in this chapter are examples only and do not provide a complete list of all possible accesses For more details on AMBA interface and integration see the AMBA specification 6 1 1 Summary of the AHB transfer mechanism An AHB transfer comprises the following Address phase This la...

Page 82: ...f burst A burst is a series of transfers The ARM720T processor performs the following types of burst Incrementing burst of unspecified length 8 beat incrementing burst only used during linefill Incrementing bursts do not wrap at address boundaries The address of each transfer in the burst is an increment of the address of the previous transfer in the burst For more information see Address and cont...

Page 83: ...control signals on page 6 7 Slave transfer response HREADY HRESP 1 0 See Slave transfer response signals on page 6 9 Data HRDATA 31 0 HWDATA 31 0 See Data buses on page 6 10 Arbitration HBUSREQ HGRANT HLOCK See Arbitration on page 6 12 Clock HCLK HCLKEN See Bus clocking on page 6 13 Reset HRESETn See Reset on page 6 13 Each of these signal groups shares a common timing relationship to the bus inte...

Page 84: ...n in Figure 6 2 Figure 6 2 AHB bus master interface AHB master HBUSREQ HLOCK HREADY HRESETn HWRITE HCLKEN HCLK HTRANS 1 0 HRDATA 31 0 HWDATA 31 0 HPROT 3 0 HBURST 2 0 HSIZE 2 0 HADDR 31 0 HRESP 1 0 HGRANT Arbiter grant Data Reset Clock Transfer type Data Address and control Arbiter Transfer response ...

Page 85: ...ransfer type is used when a bus master is granted the bus but does not wish to perform a data transfer Slaves must always provide a zero wait state OKAY response to IDLE transfers and the transfer must be ignored by the slave b10 NONSEQ Indicates the first transfer of a burst or a single transfer The address and control signals are unrelated to the previous transfer Single transfers on the bus are...

Page 86: ...the second transfer of the burst immediately The master performs the third transfer of the burst immediately but this time the slave is unable to complete and uses HREADY to insert a single wait state The final transfer of the burst completes with zero wait states NONSEQ SEQ SEQ 0x20 0x24 0x28 0x2C Data 0x28 0x20 Data 0x24 SEQ Data Data 0x2C INCR Data 0x28 0x20 Data 0x24 Data Data 0x2C HCLK HTRANS...

Page 87: ...om bit HADDR 0 6 4 2 HWRITE HWRITE specifies the direction of the transfer as follows HWRITE HIGH Indicates an ARM720T processor write cycle HWRITE LOW Indicates an ARM720T processor read cycle A burst of S cycles is always either a read burst or a write burst The direction cannot be changed in the middle of a burst 6 4 3 HSIZE 2 0 The SIZE 2 0 bus encodes the size of the transfer The ARM720T proc...

Page 88: ...th a memory management unit these signals also indicate whether the current access is cachable or bufferable Table 6 4 shows the protection control encodings as produced from the ARM720T core Some bus masters are not capable of generating accurate protection information so it is recommended that slaves do not use the HPROT 3 0 signals unless strictly necessary Table 6 3 Burst type encodings HBURST...

Page 89: ...ransfer signal an error to indicate that the transfer has failed delay the completion of the transfer but enable the master and slave to back off the bus leaving it available for other transfers 6 5 1 HREADY The HREADY signal is used to extend the data portion of an AHB transfer as follows HREADY LOW Indicates that the transfer data is to be extended It causes wait states to be inserted into the t...

Page 90: ...s For byte transfers for example 0x12 HWDATA 31 0 is driven with the value 0x12121212 regardless of endianness Table 6 5 Response encodings HRESP 1 0 Response Description b00 OKAY When HREADY is HIGH this response indicates that the transfer has completed successfully The OKAY response is also used for any additional cycles that are inserted with HREADY LOW prior to giving one of the three other r...

Page 91: ...pletes with an OKAY response on HRESP 1 0 SPLIT RETRY and ERROR responses do not require valid read data 6 6 3 Endianness It is essential that all modules are of the same endianness and also that any data routing or bridges are of the same endianness Dynamic endianness is not supported because in most embedded systems this leads to a significant silicon overhead that is redundant It is recommended...

Page 92: ...Each bus master has its own HBUSREQ signal to the arbiter and there can be up to 16 separate bus masters in any system 6 7 2 HLOCK The lock signal is asserted by a master at the same time as the bus request signal This indicates to the arbiter that the master is performing a number of indivisible transfers and the arbiter must not grant any other bus master access to the bus once the first transfe...

Page 93: ...nterface Note HCLKEN is not a clock enable for the CPU itself but only for the bus Use HREADY to insert wait states on the bus 6 9 Reset The bus reset signal is HRESETn This signal is the global reset used to reset the system and the bus It can be asserted asynchronously but is deasserted synchronously after the rising edge of HCLK Complete system reset is achieved when DBGnTRST is asserted in the...

Page 94: ...6 The Bus Interface 6 14 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 95: ...7 Memory Management Unit ...

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Page 97: ...on and data address ports of the core The MMU is controlled from a single set of two level page tables stored in main memory that are enabled by the M bit in CP15 register 1 providing a single address translation and protection scheme The MMU features are standard ARMv4 MMU mapping sizes domains and access protection scheme mapping sizes are 1MB sections 64KB large pages 4KB small pages and 1KB ti...

Page 98: ...lated entries During CPU memory accesses the TLB provides the protection information to the access control logic If the TLB contains a translated entry for the MVA the access control logic determines if access is permitted if access is permitted and an off chip access is required the MMU outputs the appropriate physical address corresponding to the MVA if access is permitted and an off chip access...

Page 99: ...nslation Table Base Register 2 31 14 Holds the physical address of the base of the translation table maintained in main memory This base address must be on a 16KB boundary Domain Access Control Register 3 31 0 Comprises 16 2 bit fields Each field defines the access control attributes for one of 16 domains D15 D0 Fault Status Register 5 7 0 Indicates the cause of a Data or Prefetch Abort and the do...

Page 100: ...tion mapped access or a page mapped access There are three sizes of page mapped accesses and one size of section mapped access The page mapped accesses are for large pages small pages tiny pages The translation process always starts out in the same way with a level one fetch A section mapped access requires only a level one fetch but a page mapped access requires a subsequent level two fetch 7 3 1...

Page 101: ...s 19 0 Section base Coarse page table 256 entries Fine page table 1024 entries Indexed by modified virtual address bits 19 12 Indexed by modified virtual address bits 19 10 Coarse page table base Fine page table base Level two fetch Large page 64 KB Small page 4 KB Tiny page 1 KB Large page base Indexed by modified virtual address bits 15 0 Indexed by modified virtual address bits 11 0 Indexed by ...

Page 102: ...scriptor Figure 7 4 Level one descriptor A section descriptor provides the base address of a 1MB block of memory The page table descriptors provide the base address of a page table that contains level two descriptors There are two sizes of page table coarse page tables have 256 entries splitting the 1MB that the table describes into 4KB blocks fine page tables have 1024 entries splitting the 1MB t...

Page 103: ... access permission bits 9 9 11 9 Should Be Zero 8 5 8 5 8 5 Domain control bits 4 4 4 Must be 1 3 2 These bits C and B indicate whether the area of memory mapped by this page is treated as cachable or noncachable and bufferable or nonbufferable The system is always write through 3 2 3 2 Should Be Zero 1 0 1 0 1 0 These bits indicate the page size and validity and are interpreted as shown in Table ...

Page 104: ...rse page table descriptor is returned from the level one fetch a level two fetch is initiated Table 7 4 Section descriptor bits Bits Description 31 20 Form the corresponding bits of the physical address for a section 19 12 Always written as 0 11 10 AP Specify the access permissions for this section 9 Always written as 0 8 5 Specify one of the 16 possible domains held in the Domain Access Control R...

Page 105: ...These bits form the base for referencing the level two descriptor the coarse page table index for the entry is derived from the MVA 9 Always written as 0 8 5 These bits specify one of the 16 possible domains held in the Domain Access Control Registers that contain the primary access controls 4 Always written as 1 3 2 Always written as 0 1 0 These bits must be 01 to indicate a coarse page table des...

Page 106: ...The page table is then accessed and a level two descriptor is returned Figure 7 9 shows the format of level two descriptors Figure 7 9 Level two descriptor 31 14 13 0 Translation base 31 14 13 2 1 0 0 0 Table index Translation base Modified virtual address Translation table base 31 20 19 0 Table index Section index 31 20 19 0 Section index Section base address Section level one descriptor Physical...

Page 107: ...he two least significant bits of the level two descriptor indicate the descriptor type as shown in Table 7 8 Note Tiny pages do not support subpage permissions and therefore only have one set of access permission bits Table 7 7 Level two descriptor bits Bits Description Large Small Tiny 31 16 31 12 31 10 These bits form the corresponding bits of the physical address 15 12 9 6 Should Be Zero 11 4 1...

Page 108: ...ncluded in a fine page table the high order six bits of the page index and low order six bits of the fine page table index overlap Each fine page table entry for a large page must therefore be duplicated 64 times 31 14 13 0 Translation base 31 14 13 2 1 0 0 0 Table index Translation base Modified virtual address Translation table base 31 20 19 0 Table index Page index Level one descriptor Physical...

Page 109: ...ex overlap Each fine page table entry for a small page must therefore be duplicated four times 31 14 13 0 Translation base 31 14 13 2 1 0 0 0 Table index Translation base Modified virtual address Translation table base 31 20 19 0 Table index Page index Level one descriptor Physical address 31 0 Coarse page table base address Domain 1 1 2 1 3 4 5 8 9 10 Level 2 table index 12 11 31 0 Page index Pag...

Page 110: ...of small and large pages If during a page walk a small or large page has a non identical subpage permission only the subpage being accessed is written into the TLB For example a 16KB large page subpage entry is written into the TLB if the subpage permission differs and a 64KB entry is put in the TLB if the subpage permissions are identical When you use subpage permissions and the page entry then h...

Page 111: ...ignment fault checking is not affected by whether or not the MMU is enabled Translation domain and permission faults are only generated when the MMU is enabled The access control mechanisms of the MMU detect the conditions that produce these faults If a fault is detected as a result of a memory access the MMU aborts the access and signals the fault condition to the CPU core The MMU retains status ...

Page 112: ...ther b0001 or b0011 into FS 3 0 Invalid values in domains 3 0 can occur because the fault is raised before a valid domain field has been read from a page table descriptor Any abort masked by the priority encoding can be regenerated by fixing the primary abort and restarting the instruction Table 7 9 Priority encoding of fault status Priority Source Size Status Domain FAR Highest Alignment b00x1 In...

Page 113: ...ister format Table 7 10 defines how the bits within each domain are interpreted to specify the access permissions Table 7 10 Interpreting access control bits in Domain Access Control Register Value Meaning Description b00 No access Any access generates a domain fault b01 Client Accesses are checked against the access permission bits in the section or page descriptor b10 Reserved Reserved Currently...

Page 114: ...ription b00 0 0 No access No access Any access generates a permission fault b00 1 0 Read only No access Only Supervisor read permitted b00 0 1 Read only Read only Any write generates a permission fault b00 1 1 Reserved a a Do not use this encoding S R b11 generates a fault for any access b01 x x Read write No access Access allowed only in Supervisor mode b10 x x Read write Read only Writes in User...

Page 115: ... not word aligned or on any halfword access if the address is not halfword aligned irrespective of whether the MMU is enabled or not An alignment fault is not generated on any instruction fetch nor on any byte access Note If the access generates an alignment fault the access sequence aborts without reference to more permission checks Modified virtual address Check address alignment Misaligned Alig...

Page 116: ...ault or page domain fault occurs 7 7 4 Permission fault If the 2 bit domain field returns 01 client then access permissions are checked as follows Section If the level one descriptor defines a section mapped access the AP bits of the descriptor define whether or not the access is allowed according to Table 7 11 on page 7 18 Their interpretation is dependent on the setting of the S and R bits contr...

Page 117: ... tables as required 3 Enable the MMU by setting bit 0 in the control register You must take care if the translated address differs from the untranslated address because several instructions following the enabling of the MMU might have been prefetched with the MMU off using physical VA flat translation In this case enabling the MMU can be considered as a branch with delayed execution A similar situ...

Page 118: ...7 Memory Management Unit 7 22 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 119: ...8 Coprocessor Interface ...

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Page 121: ...n pipeline instruction decoding logic handshake logic a register bank special processing logic with its own data path A coprocessor is connected to the same data bus as the ARM720T processor in the system and tracks the pipeline in the ARM720T core This means that the coprocessor can decode the instructions in the instruction stream and execute those that it supports Each instruction progresses do...

Page 122: ...y You can connect up to 16 coprocessors into a system each with a unique coprocessor ID number Some coprocessor numbers are reserved For example you cannot assign external coprocessors to coprocessor numbers 14 and 15 because these are internal to the ARM720T processor CP14 is the communications channel coprocessor CP15 is the system control coprocessor for cache and MMU functions Coprocessor avai...

Page 123: ... EXTCPCLKEN HRESETn The pipeline following signals are CPnMREQ CPnTRANS CPnOPC CPTBIT The handshake signals are CPnCPI EXTCPA EXTCPB The data signals are EXTCPDIN 31 0 EXTCPDOUT 31 0 EXTCPDBE These signals and their use are described in Pipeline following signals on page 8 4 Coprocessor interface handshaking on page 8 5 Connecting coprocessors on page 8 9 Not using an external coprocessor on page ...

Page 124: ...ipeline on the rising edge of HCLK and only when CPnOPC CPnMREQ and CPTBIT were all LOW in the previous bus cycle These conditions indicate that this cycle is an ARM state opcode Fetch so the new opcode must be sampled into the pipeline The pipeline must be advanced on the rising edge of HCLK when CPnOPC CPnMREQ and CPTBIT are all LOW in the current bus cycle These conditions indicate that the cur...

Page 125: ... back to the ARM720T core using EXTCPA and EXTCPB 8 4 2 The ARM720T core Coprocessor instructions progress down the ARM720T processor pipeline in step with the coprocessor pipeline A coprocessor instruction is executed if the following are true 1 The coprocessor instruction has reached the Execute stage of the pipeline It might not if it was preceded by a branch 2 The instruction has passed its co...

Page 126: ...oprocessor instruction can be interrupted If a valid FIQ or IRQ occurs the appropriate bit is cleared in the CSPR the ARM720T processor abandons the coprocessor instruction and signals this by taking CPnCPI HIGH A coprocessor that is capable of busy waiting must monitor CPnCPI to detect this condition When the ARM720T core abandons a coprocessor instruction the coprocessor also abandons the instru...

Page 127: ...processor register bank No information is transferred between the ARM720T core and the coprocessor as a result of this operation An example sequence is shown in Figure 8 3 Figure 8 3 Coprocessor data operation sequence ADD SWINE TST MCR SUB TST MCR SUB ADD SWINE MCR SUB ADD SWINE TST I Fetch I Fetch I Fetch I Fetch I Fetch I Fetch ADD SUB SWINE TST MCR HCLK Fetch stage Decode stage Execute stage C...

Page 128: ...ta in a single instruction An example sequence is shown in Figure 8 4 Note The external coprocessor must not abort on LDC and STC instructions unless they can be decoded as a CP15 operations otherwise dead lock occurs on busy waiting If you transfer more than 16 words of data in a single instruction the worst case interrupt latency of the ARM720T processor increases Figure 8 4 Coprocessor load seq...

Page 129: ... system with an ETM7 and an ARM720T core you must directly connect the following buses ETM7 input RDATA 31 0 to the ARM720T processor output ETMRDATA 31 0 ETM7 input WDATA 31 0 to the ARM720T processor output ETMWDATA 31 0 This enables the ETM to correctly trace coprocessor instructions 8 5 2 Connecting multiple coprocessors If you have multiple coprocessors in your system connect the handshake si...

Page 130: ... processor implements full ARM architecture v4T undefined instruction handling This means that any instruction defined in the ARM Architecture Reference Manual as UNDEFINED automatically causes the ARM720T processor to take the undefined instruction trap Any coprocessor instructions that are not accepted by a coprocessor also result in the ARM720T processor taking the undefined instruction trap 8 ...

Page 131: ...9 Debugging Your System ...

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Page 133: ...ode debugging 9 12 9 10 The debug communications channel 9 14 9 11 Scan chains and the JTAG interface 9 17 9 12 The TAP controller 9 19 9 13 Public JTAG instructions 9 20 9 14 Test data registers 9 22 9 15 Scan timing 9 25 9 16 Examining the core and the system in debug state 9 26 9 17 Exit from debug state 9 29 9 18 The program counter during debug 9 30 9 19 Priorities and exceptions 9 32 9 20 Wa...

Page 134: ...ue high level commands such as setting breakpoints or examining the contents of memory Protocol converter This interfaces between the high level commands issued by the debug host and the low level commands of the ARM720T processor JTAG interface Typically it interfaces to the host through an interface such as an enhanced parallel port Debug target The ARM720T processor has hardware extensions that...

Page 135: ...ns such as breakpoints This unit is described in The EmbeddedICE RT macrocell on page 9 10 TAP controller Controls the action of the scan chains using a JTAG serial interface For more details see The TAP controller on page 9 19 These blocks are shown in Figure 9 2 Figure 9 2 ARM720T processor block diagram ARM720T processor System control processor ARM720T EmbeddedICE RT Scan chain 2 Scan chain 15...

Page 136: ...hpoint or to a genuine memory abort For more information see Monitor mode debugging on page 9 12 9 2 2 Examining system state during debugging In both halt mode and monitor mode the JTAG style serial interface enables you to examine the internal state of the core and the external state of the system while system activity continues In halt mode this enables instructions to be inserted serially into...

Page 137: ...se the DBGBREAK signal to enable external logic to flag breakpoints or watchpoints and monitor the following address bus data bus control signals The timing is the same for externally generated breakpoints and watchpoints Data must always be valid around the rising edge of HCLK When this data is an instruction to be breakpointed the DBGBREAK signal must be HIGH around the rising edge of HCLK Simil...

Page 138: ... instruction pipeline and cancel the breakpoint In normal circumstances on exiting from an exception the ARM720T core branches back to the instruction that would have been executed next before the exception occurred In this case the pipeline is refilled and the breakpoint is reflagged 9 3 2 Entry into debug state on watchpoint Watchpoints occur on data accesses In halt mode the core processing sto...

Page 139: ...ion of nIRQ and nFIQ 9 3 4 Action of the ARM720T processor in debug state When the ARM720T processor enters debug state the core forces HTRANS 1 0 to indicate internal cycles This action enables the rest of the memory system to ignore the ARM720T core and to function as normal Because the rest of the system continues to operate the ARM720T core is forced to ignore aborts and interrupts Caution Do ...

Page 140: ... example Multi ICE issues a TCK signal and waits for the RTCK Returned TCK signal to come back Synchronization is maintained because the off chip device does not progress to the next TCK until after RTCK is received Figure 9 4 shows this synchronization Figure 9 4 Clock synchronization Note All the D types shown in Figure 9 4 are reset by DBGnTRST Reset circuit DBGnTRST nTRST DBGTDO TDO D Q D Q D ...

Page 141: ...te Both DBGRQ and DBGBREAK must be LOW when the core has entered debug state If they are not these signals affect the use of the DBGBREAK flag on scan chain 1 which controls the way the core goes into and out of debug The result is that the core performs an unexpected series of debug and system speed accesses and the debugger loses control of the core DBGACK is used by the ARM720T core to flag bac...

Page 142: ...oller and EmbeddedICE RT macrocell The EmbeddedICE RT logic comprises the following Two real time watchpoint units You can program one or both watchpoint units to halt the execution of instructions by the core Execution halts when the values programmed into the EmbeddedICE RT logic match the values currently appearing on the address bus data bus and various control signals You can mask any bit so ...

Page 143: ...of the EmbeddedICE RT registers are given in EmbeddedICE RT timing on page 9 44 9 7 Disabling EmbeddedICE RT You can disable EmbeddedICE RT in two ways Permanently By wiring the DBGEN input LOW When DBGEN is LOW DBGBREAK and DBGRQ are ignored by the core Note DBGACK is forced LOW by the ARM720T core interrupts pass through to the processor uninhibited the EmbeddedICE RT logic enters low power mode...

Page 144: ...that a breakpoint or watchpoint causes the ARM720T core to enter abort mode taking the Prefetch or Data Abort vectors respectively Bit 4 clear Monitor mode debugging is disabled and the system is placed into halt mode In halt mode the core enters debug state when it encounters a breakpoint or watchpoint Table 9 1 Function and mapping of EmbeddedICE RT registers Address Width Function b00000 6 Debu...

Page 145: ...in the abort status register in coprocessor 14 see Abort status register on page 9 38 The monitor mode enable bit does not put the ARM720T processor into debug state For this reason it is necessary to change the contents of the watchpoint registers while external memory accesses are taking place rather than changing them when in debug state where the core is halted If there is a possibility of fal...

Page 146: ...rs between the debugger and the processor For more details see Communications through the DCC on page 9 16 These registers occupy fixed locations in the EmbeddedICE RT memory map as shown in Table 9 1 on page 9 12 They are accessed from the processor using MCR and MRC instructions to coprocessor 14 The registers are accessed as follows By the debugger Through scan chain 2 in the usual way By the p...

Page 147: ...er into the destination register Rd Note The Thumb instruction set does not contain coprocessor instructions so it is recommended that these are accessed using SWI instructions when in Thumb state Table 9 2 Domain Access Control Register bit assignments Bit Function 31 28 Contain a fixed pattern that denotes the EmbeddedICE RT version number This must be b0111 when using MRC operation to read it b...

Page 148: ...a When the debugger sees that the W bit is set it can read the communications data write register and scan the data out b The action of reading this data register clears the W bit of the Domain Access Control Register At this point the communications process can begin again Receiving a message from the debugger Transferring a message from the debugger to the processor is similar to sending a messa...

Page 149: ...n chain 0 is not implemented in the ARM720T processor but all the control signals are provided at the macrocell boundary This enables you to design your own boundary scan chain wrapper if required Figure 9 7 ARM720T processor scan chain arrangements Scan chain 1 Scan chain 1 provides serial access to the core data bus HRDATA HWDATA and the DBGBREAK signal There are 33 bits in this scan chain the o...

Page 150: ...uction field of scan chain 15 is RAZ 9 11 2 Controlling the JTAG interface The JTAG interface is driven by the currently loaded instruction in the instruction register described in Instruction register on page 9 23 The loading of instructions is controlled by the Test Access Port TAP controller For more information about the TAP controller see The TAP controller on page 9 19 Table 9 3 Instruction ...

Page 151: ...erface is not to be used you can tie the DBGnTRST input LOW The action of reset is as follows 1 System mode is selected This means that the boundary scan cells do not intercept any of the signals passing between the external system and the core 2 The IDCODE instruction is selected When the TAP controller is put into the SHIFT DR state and HCLK is pulsed while enabled by DBGTCKEN the contents of th...

Page 152: ... scan chain 0 is selected by default The scan path select register is 4 bits long in this implementation although no finite length is specified 9 13 2 INTEST b1100 The INTEST instruction places the selected scan chain in test mode The INTEST instruction connects the selected scan chain between DBGTDI and DBGTDO When the INTEST instruction is loaded into the instruction register all the scan cells ...

Page 153: ...te the ID register is unaffected 9 13 4 BYPASS b1111 The BYPASS instruction connects a 1 bit shift register the bypass register between DBGTDI and DBGTDO When the BYPASS instruction is loaded into the instruction register all the scan cells assume their normal system mode of operation The BYPASS instruction has no effect on the system pins In the CAPTURE DR state a logic 0 is captured the bypass r...

Page 154: ...red from DBGTDI to DBGTDO in the SHIFT DR state with a delay of one HCLK cycle enabled by DBGTCKEN There is no parallel output from the bypass register A logic 0 is loaded from the parallel input of the bypass register in the CAPTURE DR state 9 14 2 ARM720T processor device identification ID code register Purpose Reads the 32 bit device identification code No programmable supplementary identificat...

Page 155: ...AN_N as the current instruction in the SHIFT DR state selects the scan path select register as the serial path between DBGTDI and DBGTDO During the CAPTURE DR state the value b1000 binary is loaded into this register This value is loaded out during SHIFT DR least significant bit first while a new value is loaded in least significant bit first During the UPDATE DR state the value in the register se...

Page 156: ...communication between the debugger and the ARM720T core It is used to read and write data and to scan instructions into the pipeline The SCAN_N TAP instruction can be used to select scan chain 1 Length 33 bits 32 bits a for the data value and 1 bit for the scan cell on the DBGBREAK core input Scan chain order From DBGTDI to DBGTDO the ARM720T processor data bits bits 0 to 31 then the 33rd bit the ...

Page 157: ...scan timing information Figure 9 10 Scan timing 9 15 1 Scan chain 1 cells The ARM720T processor provides data for scan chain 1 cells as shown in Table 9 6 Table 9 6 Scan chain 1 cells Number Signal Type 1 DATA 0 Input output 2 DATA 1 Input output 3 DATA 2 Input output 4 DATA 3 Input output 5 DATA 4 Input output 6 DATA 5 Input output 7 DATA 6 Input output 8 DATA 7 Input output 9 DATA 8 Input output...

Page 158: ...ICE RT debug status register as follows Bit 4 HIGH The core has entered debug from Thumb state Bit 4 LOW The core has entered debug from ARM state 15 DATA 14 Input output 16 DATA 15 Input output 17 DATA 16 Input output 18 DATA 17 Input output 19 DATA 18 Input output 20 DATA 19 Input output 21 DATA 20 Input output 22 DATA 21 Input output 23 DATA 22 Input output 24 DATA 23 Input output 25 DATA 24 In...

Page 159: ...n the ARM state the first instruction to execute is typically STM R0 r0 r15 This instruction causes the contents of the registers to appear on the data bus You can then sample and shift out these values Note The use of r0 as the base register for the STM is only for illustration any register can be used After you have determined the values in the current bank of registers you might wish to access ...

Page 160: ...TART instruction must be loaded into the TAP controller RESTART causes the ARM720T processor to 1 Switch automatically to HCLKEN control 2 Execute the instruction at system speed 3 Reenter debug state When the instruction has completed DBGACK is HIGH and the core reverts to DBGTCKEN control It is now possible to select INTEST in the TAP controller and resume debugging The debugger must look at bot...

Page 161: ...n fetching instructions from memory This delay until the state machine is in the RUN TEST IDLE state enables conditions to be set up in other devices in a multiprocessor system without taking immediate effect When the state machine enters the RUN TEST IDLE state all the processors resume operation simultaneously DBGACK informs the rest of the system when the ARM720T processor is in debug state Thi...

Page 162: ...tate from a breakpoint advances the PC by four addresses or 16 bytes Each instruction executed in debug state advances the PC by one address or 4 bytes The usual way to exit from debug state after a breakpoint is to remove the breakpoint and branch back to the previously breakpointed address For example if the ARM720T processor entered debug state from a breakpoint set on a given address and two d...

Page 163: ...s refetched and executed This triggers the watchpoint again and the ARM720T processor reenters debug state 9 18 4 Debug request Entry into debug state using a debug request is similar to a breakpoint However unlike a breakpoint the last instruction has completed execution and so must not be refetched on exit from debug state Therefore you can assume that entry to debug state adds three addresses t...

Page 164: ... or a debug request occurs the normal flow of the program is interrupted Therefore debug can be treated as another type of exception The interaction of the debugger with other exceptions is described in The program counter during debug on page 9 30 This section covers the following priorities Breakpoint with Prefetch Abort Interrupts Data Aborts 9 19 1 Breakpoint with Prefetch Abort When a breakpo...

Page 165: ...ode The watchpoint therefore has higher priority than the abort but the ARM720T processor remembers that the abort happened 9 20 Watchpoint unit registers There are two watchpoint units known as watchpoint 0 and watchpoint 1 You can configure either to be a watchpoint monitoring data accesses or a breakpoint monitoring instruction fetches You can make watchpoints and breakpoints data dependent Eac...

Page 166: ...canned into the 5 bit address field and the read write bit is set A register is read by shifting its address into the address field and by shifting a 0 into the read write bit The 32 bit data field is ignored The register addresses are shown in Table 9 1 on page 9 12 Note A read or write takes place when the TAP controller enters the UPDATE DR state read write 0 4 31 0 Data Scan chain register Add...

Page 167: ...ster 9 20 3 The watchpoint unit control registers The control value and control mask registers are mapped identically in the lower eight bits as shown in Figure 9 13 Figure 9 13 Watchpoint control value and mask format Bit 8 of the control value register is the ENABLE bit and cannot be masked The bits have the following functions WRITE Compares against the write signal from the core in order to de...

Page 168: ... occurs the internal DBGBREAK signal is asserted only when the ENABLE bit is set This bit exists only in the value register It cannot be masked For each of the bits 7 0 in the control value register there is a corresponding bit in the control mask register This removes the dependency on particular signals 9 21 Programming breakpoints Breakpoints are classified as hardware breakpoints or software b...

Page 169: ...ss is disregarded 2 Program the data value register with the particular bit pattern that has been chosen to represent a software breakpoint If you are programming a Thumb software breakpoint repeat the 16 bit pattern in both halves of the data value register For example if the bit pattern is 0xDFFF program 0xDFFFDFFF When a 16 bit instruction is fetched EmbeddedICE RT compares only the valid half ...

Page 170: ...with the value corresponding to the appropriate data size 5 Program the control mask register as follows PROT 0 Clear HWRITE Clear Note You can set this bit if both reads and writes are to be watchpointed SIZE 1 0 Clear Note You can set these bits if data size accesses are to be watchpointed All other bits Set 6 If you have to make the distinction between User and non User mode data accesses progr...

Page 171: ... be read and written through JTAG Set bit 5 when programming breakpoint or watchpoint registers changing bit 4 of the Debug Control Register You must clear bit 5 after you have made the changes to re enable the EmbeddedICE RT logic and make the new breakpoints and watchpoints operational 4 Used to determine the behavior of the core when breakpoints or watchpoints are reached If clear the core ente...

Page 172: ... only opens when the TAP controller state machine is in the RUN TEST IDLE state This enables an enter debug condition to be set up in all the processors in the system while they are still running When the condition is set up in all the processors it can be applied to them simultaneously by entering the RUN TEST IDLE state 9 24 3 Forcing DBGACK Figure 9 17 on page 9 42 shows that the value of the i...

Page 173: ... bit assignments Bit Function 12 Enables the debugger to determine whether the core has entered debug state due to the assertion of DBGRQ 4 Enables TBIT to be read This enables the debugger to determine what state the processor is in and which instructions to execute 3 Enables the state of the HTRANS 1 signal from the core to be read This enables the debugger to determine whether a memory access f...

Page 174: ...ure 9 17 Figure 9 17 Debug control and status register structure Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 0 Bit 2 Bit 1 Debug control register Debug status register TBIT from core TRANS 1 from core DBGACKI from core Interrupt mask enable to core DBGRQ from ARM720T input DBGACKI from core DBGACK to ARM720T processor output DBGRQI to core ...

Page 175: ...Am 31 0 Cm 4 0 0xFFFFFFFFF CHAINOUT Dv 31 0 Cv 6 4 XNOR D 31 0 C 7 5 OR Dm 31 0 Cm 7 5 0x7FFFFFFFF The CHAINOUT output of watchpoint register 1 provides the CHAIN input to Watchpoint 0 This CHAIN input enables you to use quite complicated configurations of breakpoints and watchpoints Note There is no CHAIN input to Watchpoint 1 and no CHAIN output from Watchpoint 0 For example consider the request...

Page 176: ...rogram the watchpoint registers as follows For Watchpoint 1 1 Program Watchpoint 1 with an address value of 0x00000000 and an address mask of 0x0000001F 2 Clear the ENABLE bit 3 Program all other Watchpoint 1 registers as normal for a breakpoint An address within the first 32 bytes causes the RANGE output to go HIGH but does not trigger the breakpoint For Watchpoint 0 1 Program Watchpoint 0 with a...

Page 177: ...10 ETM Interface ...

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Page 179: ...tem each processor must have its own dedicated ETM See the ETM7 Rev 1 Technical Reference Manual for detailed information about integrating an ETM7 with an ARM720T processor 10 2 Enabling and disabling the ETM7 interface Under the control of the ARM debug tools the ETM7 PWRDOWN output is used to enable and disable the ETM When PWRDOWN is HIGH this indicates that the ETM is not currently enabled so...

Page 180: ...ell signal name ARM720T processor signal name A 31 0 ETMADDR 31 0 ABORT ETMABORT ARMTDO DBGTDO BIGEND ETMBIGEND CLKa HCLKa CLKEN ETMCLKEN CPA ETMCPA CPB ETMCPB DBGACK ETMDBGACK DBGRQb DBGRQb nMREQ ETMnMREQ SEQ ETMSEQ MAS 1 0 ETMSIZE 1 0 nCPI ETMnCPI nEXEC ETMnEXEC nOPC ETMnOPC nRESET HRESETn nRW ETMnRW nTRSTa DBGnTRSTa PROCID 31 0 ETMPROCID 31 0 PROCIDWR ETMPROCIDWR ETMEN or inverted PWRDOWN ETMEN...

Page 181: ...M720T processor If this input is already in use you can OR the DBGRQ inputs together See the ETM7 Technical Reference Manual for more details 10 6 TAP interface wiring The ARM720T processor does not provide a scan chain expansion input ARM Limited recommends that you connect the ARM720T processor and the ETM7 TAP controllers in parallel For more details see the ETM7 Rev 1 Technical Reference Manua...

Page 182: ...10 ETM Interface 10 4 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 183: ...11 Test Support ...

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Page 185: ...ocessor 15 register c15 of the ARM720T processor is used to provide device specific test operations You can use it to access and control the following Test State Register on page 11 3 Cache test registers and operations on page 11 3 MMU test registers and operations on page 11 8 You must only use these operations for test The ARM Architecture Reference Manual describes this register as implementat...

Page 186: ...G test signals Test signals Direction Description TESTENABLE Input This signal ensures the clocks are free running during scan test TESTENABLE must be tied HIGH throughout the duration of scan testing tied LOW during functional mode SCANENABLE Input This signal enables serial shifting of vectors through the scan chains You must control this signal using the I O pins It must be tied LOW during func...

Page 187: ... cache entirely in software CP15 register c7 is write only and provides only one function invalidate cache The CP15 register c9 operations are read and write The operations available are write victim and lockdown base write victim The CP15 register c15 operations are write to register C15 C read from register C15 C CAM read to C15 C CAM write RAM read to C15 C RAM write from C15 C CAM match RAM re...

Page 188: ...gister c7 c9 and c15 operations Function Rd Instruction Invalidate cache SBZ MCR p15 0 Rd c7 c7 0 Write cache victim and lockdown base Victim Base MCR p15 0 Rd c9 c0 0 Write cache victim Victim Seg MCR p15 0 Rd c9 c1 0 CAM read to C15 C Seg MCR p15 2 Rd c15 c7 2 CAM write Tag Seg Dirty MCR p15 2 Rd c15 c7 6 RAM read to C15 C Seg Word MCR p15 2 Rd c15 c11 2 RAM write from C15 C Seg Word MCR p15 2 R...

Page 189: ... read format for Rd is shown in Figure 11 6 Figure 11 6 Rd format CAM match RAM read The CAM read format for data is shown in Figure 11 7 Figure 11 7 Data format CAM read The RAM read format for data is shown in Figure 11 8 Figure 11 8 Data format RAM read SBZ Word Seg 31 7 6 5 4 0 SBZ 2 1 SBZ Seg 31 7 6 5 4 0 SBZ 2 1 Word SBZ Seg 31 7 6 5 4 0 MVA TAG 2 1 Word 0 31 7 6 5 4 0 MVA TAG De Do WB 0 1 2...

Page 190: ...of the CAM and RAM for an entire segment The write cache victim and lockdown operations are shown in Table 11 4 The write cache victim and lockdown base format for Rd is shown in Figure 11 10 Figure 11 10 Rd format write cache victim and lockdown base The write cache victim format for Rd is shown in Figure 11 11 Figure 11 11 Rd format write cache victim Another cache test register C15 C is written...

Page 191: ...eset victim pointer to index 0 segment 2 MOV r0 0 ORR r1 r0 2 SHL 0x5 MCR p15 0 r1 c9 c1 0 MOV r8 64 MOV r3 0x40 read segment 2 BIC r2 r2 0x60 clear bit 5 and 6 always read as 0 loop1 MCR p15 3 r0 c15 c3 0 write C15 C to 0 MCR p15 2 r3 c15 c7 2 read CAM to C15 C MRC p15 3 r4 c15 c3 0 read C15 C to R4 BIC r4 r4 1 clear LFSR bit CMP r4 r2 BNE TEST_FAIL SUBS r8 r8 1 BNE loop1 B TEST_PASS RAM write re...

Page 192: ...operations are write Translation Table Base Registers read Translation Table Base Register The CP15 register c3 operations control the Domain Access Control DAC register These operations are write DAC registers read DAC register The CP15 register c5 operations control the Fault Status Register FSR These operations are write FSR read FSR The CP15 register c6 operations control the Fault Address Reg...

Page 193: ...e PA Tag Size PA Tag Size CAM match RAM1 read to C15 M MVA Fault Miss Protection Table 11 6 Register c2 c3 c5 c6 c8 c10 and c15 operations Function Rd Instruction s Read Translation Table Base Register TTB MRC p15 0 Rd c2 c0 0 Write Translation Table Base Register TTB MCR p15 0 Rd c2 c0 0 Read domain 15 0 access control DAC MRC p15 0 Rd c3 c0 0 Write domain 15 0 access control DAC MCR p15 0 Rd c3 ...

Page 194: ...M1 writes Figure 11 13 Rd format RAM1 write RAM1 write Protection MCR p15 4 Rd c15 c11 0 RAM2 read to C15 M SBZ MCR p15 4 Rd c15 c3 5 RAM2 write PA Tag Size MCR p15 4 Rd c15 c3 1 CAM match RAM1 read to C15 M MVA MCR p15 4 Rd c15 c13 4 Read C15 M Data MRC p15 4 Rd c15 c3 0 Table 11 7 CAM memory region size SIZE_C 3 0 Memory region size b1111 1MB b0111 64KB b0011 16KB b0001 4KB b0000 1KB Table 11 6 ...

Page 195: ... apply Figure 11 15 shows the Rd format for RAM2 writes and the data format for RAM2 reads Figure 11 15 Rd format RAM2 write and data format RAM2 read Table 11 8 Access permission bit setting AP 3 0 Access permission bits b1000 b11 b0100 b10 b0010 b01 b0001 b00 Table 11 9 Miss and fault encoding Prot fault Domain fault TLB miss Function 0 0 0 Hit OK 0 1 0 Hit domain fault 1 0 0 Hit protection faul...

Page 196: ... the victim pointer so you must write this before any CAM or RAM1 operation RAM2 uses a pipelined version of the victim pointer used for the CAM or RAM1 operation This means that to read from index N in the RAM2 array you must first perform an access to index N in either the CAM or RAM1 The write TLB lockdown operation is MCR p15 0 Rd c10 c0 0 The write TLB lockdown format for Rd is shown in Figur...

Page 197: ...0x0025A5A5 LDR r4 0xF0F0F0C0 MOV r5 64 Write all 64 lines loop0 MCR p15 4 r2 c15 c7 0 write CAM MCR p15 4 r3 c15 c11 0 write RAM1 MCR p15 4 r4 c15 c3 1 write RAM2 pointer auto incremented here SUBS r5 r5 1 BNE loop0 Now read and check Reset victim pointer MOV r0 0 MCR p15 0 r0 c10 c0 0 MOV r8 64 loop1 MCR p15 4 r5 c15 c7 4 read CAM to C15 M MRC p15 4 r5 c15 c3 6 read C15 M to R5 MCR p15 4 r6 c15 c...

Page 198: ...11 Test Support 11 14 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 199: ...Appendix A Signal Descriptions ...

Page 200: ......

Page 201: ...name Type Description HCLK Input Bus clock This is the only clock on the ARM720T processor HADDR 31 0 Output 32 bit system address bus HTRANS 1 0 Output Indicates type of current transfer HBURST 2 0 Output Indicates burst length of current transfer HWRITE Output Indicates direction of current transfer HSIZE 2 0 Output Indicates size of current transfer HPROT 3 0 Output Protection control signals H...

Page 202: ... signal indicates that the processor is fetching an instruction from memory When HIGH data if present is being transferred This signal is used by the coprocessor to track the ARM pipeline CPTBIT Output Thumb state This signal when HIGH indicates that the processor is executing the THUMB instruction set When LOW the processor is executing the ARM instruction set CPnTRANS Output Not coprocessor tran...

Page 203: ...s signal is the serial data from an external scan chain It enables a single DBGTDO port to be used If an external scan chain is not connected this input must be tied LOW DBGTAPSM 3 0 Output Tap controller status These signals represent the current state of the TAP controller machine These signals change on the rising edge of XTCK and can be used to allow more scan chains to be added using the ARM7...

Page 204: ...put is tied LOW COMMRX Output Communication receive full When HIGH this signal denotes that the comms channel receive buffer contains data for the core to read COMMTX Output Communication transmit empty When HIGH this signal denotes that the comms channel transmit buffer is empty DBGACK Output Debug acknowledge When HIGH this signal denotes that the ARM is in debug state DBGEN Input Debug enable A...

Page 205: ...it is not being executed For example it might have failed the condition check code ETMnCPI Output Not coprocessor instruction When the ARM720T processor executes a coprocessor instruction it takes the ETMnCPI LOW and waits for a response from the coprocessor The actions taken depend on this response which the coprocessor signals on the CPA and CPB inputs ETMADDR 31 0 Output Addresses This is the r...

Page 206: ...When HIGH the exception vectors start at address 0xFFFF0000 ETMSIZE 1 0 Output The memory access size bus driven by the ARM720T processor ETMRDATA 31 0 Output The processor read data bus ETMWDATA 31 0 Output The processor write data bus ETMINSTRVALID Output The instruction valid signal driven by the ARM720T processor When HIGH it indicates that the instruction in the Execute stage is valid and has...

Page 207: ...EN Input Synchronous enable for AHB transfers When HIGH indicates that the next rising edge of HCLK is also a rising edge for the AHB system that the ARM720T processor is embedded in Must be tied HIGH in systems where the AMBA bus and the core are intended to be the same frequency DBGTCKEN Input Synchronous enable for debug logic Must be tied HIGH during scan test HRESETn Input This is the active ...

Page 208: ...A Signal Descriptions A 8 EPSON ARM720T CORE CPU MANUAL THIS PAGE IS BLANK ...

Page 209: ...Glossary ...

Page 210: ......

Page 211: ...o be used as operands by data processing instructions Arithmetic Logic Unit The part of a computer that performs all arithmetic computations such as addition and multiplication and all comparison operations ALU See Arithmetic Logic Unit ARM state A processor that is executing ARM 32 bit instructions is operating in ARM state Big endian Memory organization where the least significant byte of a word...

Page 212: ... A processor enters debug state from halt mode and not from monitor mode Debugger A debugging system which includes a program used to detect locate and correct software faults together with custom hardware that supports software debugging EmbeddedICE The EmbeddedICE logic is controlled via the JTAG test access port using a protocol converter such as MultiICE an extra piece of hardware that allows ...

Page 213: ...ction Group The name of the organization that developed standard IEEE 1149 1 This standard defines a boundary scan architecture used for in circuit testing of integrated circuit devices JTAG See Joint Test Action Group Link register This register holds the address of the next instruction after a branch with link instruction Little endian memory Memory organization where the most significant byte o...

Page 214: ...instructions after the current instruction Program Status Register Contains some information about the current program and some information about the current processor Also referred to as Processor Status Register Also referred to as Current PSR CPSR to emphasize the distinction between it and the Saved PSR SPSR The SPSR holds the value the PSR had when the current function was called and which wi...

Page 215: ...ro fields Should Be Zero fields Should be written as zero or all 0s for bit fields by software Values other than zero produce Unpredictable results See also Should Be One fields Software Interrupt Instruction This instruction SWI enters Supervisor mode to request a particular operating system function SPSR See Saved Program Status Register Stack pointer A register or variable pointing to the top o...

Page 216: ...essor that is executing Thumb 16 bit instructions is operating in Thumb state UND See Undefined Undefined Indicates an instruction that generates an undefined instruction trap UNP See Unpredictable Unpredictable Means the result of an instruction cannot be relied upon Unpredictable instructions must not halt or hang the processor or any parts of the system Unpredictable fields Do not contain valid...

Page 217: ...Index ...

Page 218: ......

Page 219: ...r 9 21 9 22 Byte data type 2 3 C Cache test register 11 3 CAPTURE DR state 9 20 CHAIN bit 9 36 Clock domains 9 9 system 9 8 test 9 8 Coarse page table descriptor 7 8 Communications channel message transfer from the de bugger 9 16 Condition code flags 2 8 Configuration compatibility 3 1 description 3 1 notation 3 1 Connecting an ETM7 macrocell 10 2 Control mask 9 33 9 35 Control mask register 9 33 ...

Page 220: ...7 9 FIQ mode 2 4 definition 2 12 FIQ valid 8 6 FSR 7 16 G Grant signal AHB 6 12 H Halt mode 9 4 9 5 Hardware breakpoints 9 36 HBUSREQx 6 12 HGRANTx 6 12 High register accessing from THUMB state 2 7 description 2 7 HLOCKx 6 12 HRDATA 6 11 HRESP 6 10 HWDATA 6 10 I ID register 9 19 9 21 9 22 IDC cachable bit 4 1 disable 4 2 enable 4 2 operation 4 1 read lock write 4 2 reset 4 2 validity 4 2 double ma...

Page 221: ...7 Translation Table Base Regis ter 3 5 7 4 watchpoint 9 33 programming and reading 9 33 Registers debug address mask 9 37 BYPASS 9 21 bypass 9 22 control mask 9 33 9 35 control value 9 33 9 35 data mask 9 33 data value 9 33 EmbeddedICE RT 9 24 accessing 9 17 9 24 debug status 9 26 ID 9 22 instruction 9 20 9 21 9 22 9 23 scan path select 9 22 9 23 scan path select register 9 20 status 9 41 status r...

Page 222: ...anslating page tables 7 5 Translation faults 7 15 7 20 Translation Table Base Register TTB 7 4 U Undefined instruction handling 8 10 trap 8 10 Undefined instruction trap 2 13 Undefined mode 2 4 UPDATE DR 9 20 UPDATE IR 9 23 User mode 2 4 W Watchpoint 9 5 9 6 9 10 9 24 9 30 9 43 aborted 9 31 coupling 9 43 EmbeddedICE RT 9 36 externally generated 9 5 programming 9 38 register 9 33 9 37 registers 9 3...

Page 223: ...cio Testa Adva Alcalde Barrils num 64 68 E 08190 Sant Cugat del Vallès SPAIN Phone 34 93 544 2490 Fax 34 93 544 2491 Scotland Design Center Integration House The Alba Campus Livingston West Lothian EH54 7EG SCOTLAND Phone 44 1506 605040 Fax 44 1506 605041 ASIA EPSON CHINA CO LTD 23F Beijing Silver Tower 2 North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107319 SHANGHAI BRA...

Page 224: ...ronic Devices Website ELECTRONIC DEVICES MARKETING DIVISION http www epsondevice com Issue April 2004 Printed in Japan C A Document code 405003400 CORE CPU MANUAL ARM720T Revision 4 AMBA AHB Bus Interface Version CORE CPU MANUAL ARM720T Revision 4 AMBA AHB Bus Interface Version ...

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